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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +09002/*
3 * Configuation settings for the sh7753evb board
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +09006 */
7
8#ifndef __SH7753EVB_H
9#define __SH7753EVB_H
10
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090011#define CONFIG_CPU_SH7753 1
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090012
Vladimir Zapolskiy5e72b842016-11-28 00:15:30 +020013#define CONFIG_DISPLAY_BOARDINFO
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090014
15/* MEMORY */
16#define SH7753EVB_SDRAM_BASE (0x40000000)
17#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
18
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090019#define CONFIG_SYS_PBSIZE 256
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090020#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
21
22/* SCIF */
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090023#define CONFIG_CONS_SCIF2 1
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090024
25#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
26#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
27 480 * 1024 * 1024)
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090028#undef CONFIG_SYS_MEMTEST_SCRATCH
29#undef CONFIG_SYS_LOADS_BAUD_CHANGE
30
31#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
32#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
33#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
34 128 * 1024 * 1024)
35
36#define CONFIG_SYS_MONITOR_BASE 0x00000000
37#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
38#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
39#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
40
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090041/* Ether */
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090042#define CONFIG_SH_ETHER_USE_PORT 0
43#define CONFIG_SH_ETHER_PHY_ADDR 18
44#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
45#define CONFIG_SH_ETHER_USE_GETHER 1
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090046#define CONFIG_BITBANGMII
47#define CONFIG_BITBANGMII_MULTI
48#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
49#define CONFIG_PHY_VITESSE
50
51#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
52#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
53#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
54#define SH7753EVB_ETHERNET_MAC_SIZE 17
55#define SH7753EVB_ETHERNET_NUM_CH 2
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090056
57/* SPI */
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090058#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090059
60/* MMCIF */
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090061#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
62#define CONFIG_SH_MMCIF_CLK 48000000
63
64/* ENV setting */
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090065#define CONFIG_ENV_OVERWRITE 1
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090066#define CONFIG_EXTRA_ENV_SETTINGS \
67 "netboot=bootp; bootm\0"
68
69/* Board Clock */
70#define CONFIG_SYS_CLK_FREQ 48000000
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090071#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Yoshihiro Shimoda95abe5f2013-12-18 16:03:44 +090072#endif /* __SH7753EVB_H */