Simon Glass | aa5121f | 2014-06-02 22:04:48 -0600 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Common functions for OMAP4/5 based boards |
| 4 | * |
| 5 | * (C) Copyright 2010 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Author : |
| 9 | * Aneesh V <aneesh@ti.com> |
| 10 | * Steve Sakoman <steve@sakoman.com> |
| 11 | * |
| 12 | * SPDX-License-Identifier: GPL-2.0+ |
| 13 | */ |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <asm/cache.h> |
| 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
| 20 | #define ARMV7_DCACHE_WRITEBACK 0xe |
| 21 | #define ARMV7_DOMAIN_CLIENT 1 |
| 22 | #define ARMV7_DOMAIN_MASK (0x3 << 0) |
| 23 | |
| 24 | void enable_caches(void) |
| 25 | { |
| 26 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 27 | dcache_enable(); |
| 28 | } |
| 29 | |
| 30 | void dram_bank_mmu_setup(int bank) |
| 31 | { |
| 32 | bd_t *bd = gd->bd; |
| 33 | int i; |
| 34 | |
| 35 | u32 start = bd->bi_dram[bank].start >> 20; |
| 36 | u32 size = bd->bi_dram[bank].size >> 20; |
| 37 | u32 end = start + size; |
| 38 | |
| 39 | debug("%s: bank: %d\n", __func__, bank); |
| 40 | for (i = start; i < end; i++) |
| 41 | set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); |
| 42 | } |
| 43 | |
| 44 | void arm_init_domains(void) |
| 45 | { |
| 46 | u32 reg; |
| 47 | |
| 48 | reg = get_dacr(); |
| 49 | /* |
| 50 | * Set DOMAIN to client access so that all permissions |
| 51 | * set in pagetables are validated by the mmu. |
| 52 | */ |
| 53 | reg &= ~ARMV7_DOMAIN_MASK; |
| 54 | reg |= ARMV7_DOMAIN_CLIENT; |
| 55 | set_dacr(reg); |
| 56 | } |