| Parthiban Nallathambi | deee8c2 | 2019-11-04 19:50:07 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2019 PHYTEC Messtechnik GmbH |
| 4 | * Author: Stefan Riedmueller <s.riedmueller@phytec.de> |
| 5 | */ |
| 6 | |
| 7 | #include "imx6ul-phytec-segin.dtsi" |
| 8 | |
| 9 | / { |
| 10 | model = "PHYTEC phyBOARD-Segin i.MX6 ULL"; |
| 11 | compatible = "phytec,imx6ull-pbacd-10", "phytec,imx6ull-pcl063","fsl,imx6ull"; |
| 12 | }; |
| 13 | |
| 14 | &iomuxc { |
| 15 | /delete-node/ flexcan1engrp; |
| 16 | /delete-node/ rtcintgrp; |
| 17 | /delete-node/ stmpegrp; |
| 18 | }; |
| 19 | |
| 20 | &iomuxc_snvs { |
| 21 | princtrl_flexcan1_en: flexcan1engrp { |
| 22 | fsl,pins = < |
| 23 | MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 |
| 24 | >; |
| 25 | }; |
| 26 | |
| 27 | pinctrl_rtc_int: rtcintgrp { |
| 28 | fsl,pins = < |
| 29 | MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 |
| 30 | >; |
| 31 | }; |
| 32 | |
| 33 | pinctrl_stmpe: stmpegrp { |
| 34 | fsl,pins = < |
| 35 | MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 |
| 36 | >; |
| 37 | }; |
| 38 | }; |