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git01.mediatek.com / filogic / uboot / 3405e9ced6d5de758c63e4a1b203a7743ef9a08b / . / arch / arm / dts / k3-am642-evm-u-boot.dtsi
blob: d06955dfbc60b464584f20f1dadfa1aee21f858a [file] [log] [blame]
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]8/ {
9 chosen {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]10 tick-timer = &main_timer0;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]11 };
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]12
13 memory@80000000 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]14 bootph-all;
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]15 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]16};
17
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]18&cbass_main {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]19 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]20};
21
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]22&main_timer0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]23 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]24 clock-frequency = <200000000>;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]25};
26
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]27&main_conf {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]28 bootph-all;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]29 chipid@14 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]30 bootph-all;
Lokesh Vutla882c7dd2021-05-06 16:44:56 +0530[diff] [blame]31 };
32};
33
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]34&main_pmx0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]35 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]36};
37
38&main_i2c0_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]39 bootph-all;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]40};
41
42&main_i2c0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]43 bootph-all;
Lokesh Vutla11ba7c22021-05-06 16:44:58 +0530[diff] [blame]44};
45
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]46&main_uart0_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]47 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]48};
49
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]50&main_uart0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]51 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]52};
53
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]54&usb0 {
55 dr_mode="peripheral";
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]56 bootph-all;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]57};
58
59&usbss0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]60 bootph-all;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]61};
62
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]63&main_mmc1_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]64 bootph-all;
Aswath Govindraju1786a7f2021-08-09 22:32:23 +0530[diff] [blame]65};
66
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]67&main_usb0_pins_default {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]68 bootph-all;
Aswath Govindraju79087742021-06-04 22:00:37 +0530[diff] [blame]69};
70
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]71&dmss {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]72 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]73};
74
75&secure_proxy_main {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]76 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]77};
78
79&dmsc {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]80 bootph-all;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]81 k3_sysreset: sysreset-controller {
82 compatible = "ti,sci-sysreset";
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]83 bootph-all;
Suman Annace4e5662021-05-13 20:10:56 -0500[diff] [blame]84 };
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]85};
86
87&k3_pds {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]88 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]89};
90
91&k3_clks {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]92 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]93};
94
95&k3_reset {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]96 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]97};
98
99&sdhci0 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]100 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]101};
102
103&sdhci1 {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]104 bootph-all;
Dave Gerlach278e7ac2021-04-23 11:27:46 -0500[diff] [blame]105};
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]106
107&cpsw3g {
Roger Quadros3405e9c2023-09-29 16:46:41 +0300[diff] [blame^]108 bootph-all;
Vignesh Raghavendra759316f2021-05-10 20:06:12 +0530[diff] [blame]109};
110
111&cpsw_port2 {
112 status = "disabled";
113};