blob: ca5facb7fe71b5b20c325bfed3ef36bd5fa557b9 [file] [log] [blame]
Stephen Warrenc7382852012-05-21 10:04:27 +00001/dts-v1/;
2
3/include/ ARCH_CPU_DTS
4
5/ {
Allen Martin55d98a12012-08-31 08:30:00 +00006 model = "NVIDIA Tegra20 Harmony evaluation board";
Stephen Warrenc7382852012-05-21 10:04:27 +00007 compatible = "nvidia,harmony", "nvidia,tegra20";
8
9 aliases {
10 usb0 = "/usb@c5008000";
11 };
12
13 memory {
14 reg = <0x00000000 0x40000000>;
15 };
16
17 clocks {
18 clk_32k: clk_32k {
19 clock-frequency = <32000>;
20 };
21 osc {
22 clock-frequency = <12000000>;
23 };
24 };
25
26 clock@60006000 {
27 clocks = <&clk_32k &osc>;
28 };
29
30 serial@70006300 {
31 clock-frequency = < 216000000 >;
32 };
33
34 i2c@7000c000 {
35 status = "disabled";
36 };
37
38 i2c@7000c400 {
39 status = "disabled";
40 };
41
42 i2c@7000c500 {
43 status = "disabled";
44 };
45
46 i2c@7000d000 {
47 status = "disabled";
48 };
49
50 usb@c5000000 {
51 status = "disabled";
52 };
53
54 usb@c5004000 {
55 status = "disabled";
56 };
Stephen Warren560a1ee2012-07-30 07:37:52 +000057
58 nand-controller@70008000 {
59 nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
60 nvidia,width = <8>;
61 nvidia,timing = <26 100 20 80 20 10 12 10 70>;
62 nand@0 {
63 reg = <0>;
64 compatible = "hynix,hy27uf4g2b", "nand-flash";
65 };
66 };
Stephen Warrenc7382852012-05-21 10:04:27 +000067};