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git01.mediatek.com / filogic / uboot / 12985f823b3d67f3fceb871111507b51a25a750c / . / board / amcc / makalu / init.S
blob: 806f5fdee2ea1f48d8d1274347571dc0e4b6215a [file] [log] [blame]
Stefan Roesee3c73582007-10-22 07:34:34 +0200[diff] [blame]1/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Based on code provided from Senao and AMCC
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <ppc4xx.h>
28
29#include <ppc_asm.tmpl>
30#include <ppc_defs.h>
31
32#define mtsdram_as(reg, value) \
33 addi r4,0,reg ; \
34 mtdcr memcfga,r4 ; \
35 addis r4,0,value@h ; \
36 ori r4,r4,value@l ; \
37 mtdcr memcfgd,r4 ;
38
39 .globl ext_bus_cntlr_init
40ext_bus_cntlr_init:
41
42 /*
43 * DDR2 setup
44 */
45
46 /* Following the DDR Core Manual, here is the initialization */
47
48 /* Step 1 */
49
50 /* Step 2 */
51
52 /* Step 3 */
53
54 /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
55 mtsdram_as(SDRAM_MB0CF, 0x00005201);
56
57 /* SET SDRAM_MB1CF - Not enabled */
58 mtsdram_as(SDRAM_MB1CF, 0x00000000);
59
60 /* SET SDRAM_MB2CF - Not enabled */
61 mtsdram_as(SDRAM_MB2CF, 0x00000000);
62
63 /* SET SDRAM_MB3CF - Not enabled */
64 mtsdram_as(SDRAM_MB3CF, 0x00000000);
65
66 /* SDRAM_CLKTR: Adv Addr clock by 90 deg */
67 mtsdram_as(SDRAM_CLKTR,0x80000000);
68
69 /* Refresh Time register (0x30) Refresh every 7.8125uS */
70 mtsdram_as(SDRAM_RTR, 0x06180000);
71
72 /* SDRAM_SDTR1 */
73 mtsdram_as(SDRAM_SDTR1, 0x80201000);
74
75 /* SDRAM_SDTR2 */
76 mtsdram_as(SDRAM_SDTR2, 0x32204232);
77
78 /* SDRAM_SDTR3 */
79 mtsdram_as(SDRAM_SDTR3, 0x080b0d1a);
80
81 mtsdram_as(SDRAM_MMODE, 0x00000442);
82 mtsdram_as(SDRAM_MEMODE, 0x00000404);
83
84 /* SDRAM0_MCOPT1 (0X20) No ECC Gen */
85 mtsdram_as(SDRAM_MCOPT1, 0x04322000);
86
87 /* NOP */
88 mtsdram_as(SDRAM_INITPLR0, 0xa8380000);
89 /* precharge 3 DDR clock cycle */
90 mtsdram_as(SDRAM_INITPLR1, 0x81900400);
91 /* EMR2 twr = 2tck */
92 mtsdram_as(SDRAM_INITPLR2, 0x81020000);
93 /* EMR3 twr = 2tck */
94 mtsdram_as(SDRAM_INITPLR3, 0x81030000);
95 /* EMR DLL ENABLE twr = 2tck */
96 mtsdram_as(SDRAM_INITPLR4, 0x81010404);
97 /* MR w/ DLL reset
98 * Note: 5 is CL. May need to be changed
99 */
100 mtsdram_as(SDRAM_INITPLR5, 0x81000542);
101 /* precharge 3 DDR clock cycle */
102 mtsdram_as(SDRAM_INITPLR6, 0x81900400);
103 /* Auto-refresh trfc = 26tck */
104 mtsdram_as(SDRAM_INITPLR7, 0x8D080000);
105 /* Auto-refresh trfc = 26tck */
106 mtsdram_as(SDRAM_INITPLR8, 0x8D080000);
107 /* Auto-refresh */
108 mtsdram_as(SDRAM_INITPLR9, 0x8D080000);
109 /* Auto-refresh */
110 mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
111 /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
112 mtsdram_as(SDRAM_INITPLR11, 0x81000442);
113 mtsdram_as(SDRAM_INITPLR12, 0x81010780);
114 mtsdram_as(SDRAM_INITPLR13, 0x81010400);
115 mtsdram_as(SDRAM_INITPLR14, 0x00000000);
116 mtsdram_as(SDRAM_INITPLR15, 0x00000000);
117
118 /* SET MCIF0_CODT Die Termination On */
119 mtsdram_as(SDRAM_CODT, 0x0080f837);
120 mtsdram_as(SDRAM_MODT0, 0x01800000);
121#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */
122 mtsdram_as(SDRAM_MODT1, 0x00000000);
123#endif
124
125 mtsdram_as(SDRAM_WRDTR, 0x00000000);
126
127 /* SDRAM0_MCOPT2 (0X21) Start initialization */
128 mtsdram_as(SDRAM_MCOPT2, 0x20000000);
129
130 /* Step 5 */
131 lis r3,0x1 /* 400000 = wait 100ms */
132 mtctr r3
133
134pll_wait:
135 bdnz pll_wait
136
137 /* Step 6 */
138
139 /* SDRAM_DLCR */
140 mtsdram_as(SDRAM_DLCR, 0x030000a5);
141
142 /* SDRAM_RDCC */
143 mtsdram_as(SDRAM_RDCC, 0x40000000);
144
145 /* SDRAM_RQDC */
146 mtsdram_as(SDRAM_RQDC, 0x80000038);
147
148 /* SDRAM_RFDC */
149 mtsdram_as(SDRAM_RFDC, 0x00000209);
150
151 /* Enable memory controller */
152 mtsdram_as(SDRAM_MCOPT2, 0x28000000);
153
154 blr