| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 1 | /* |
| Rajeshwari Shinde | dad39d4 | 2012-05-21 16:38:03 +0530 | [diff] [blame] | 2 | * SAMSUNG EXYNOS USB HOST EHCI Controller |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2012 Samsung Electronics Co.Ltd |
| 5 | * Vivek Gautam <gautam.vivek@samsung.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 20 | * MA 02110-1301 USA |
| 21 | */ |
| 22 | |
| Rajeshwari Shinde | dad39d4 | 2012-05-21 16:38:03 +0530 | [diff] [blame] | 23 | #ifndef __ASM_ARM_ARCH_EHCI_H__ |
| 24 | #define __ASM_ARM_ARCH_EHCI_H__ |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 25 | |
| 26 | #define CLK_24MHZ 5 |
| 27 | |
| 28 | #define HOST_CTRL0_PHYSWRSTALL (1 << 31) |
| 29 | #define HOST_CTRL0_COMMONON_N (1 << 9) |
| 30 | #define HOST_CTRL0_SIDDQ (1 << 6) |
| 31 | #define HOST_CTRL0_FORCESLEEP (1 << 5) |
| 32 | #define HOST_CTRL0_FORCESUSPEND (1 << 4) |
| 33 | #define HOST_CTRL0_WORDINTERFACE (1 << 3) |
| 34 | #define HOST_CTRL0_UTMISWRST (1 << 2) |
| 35 | #define HOST_CTRL0_LINKSWRST (1 << 1) |
| 36 | #define HOST_CTRL0_PHYSWRST (1 << 0) |
| 37 | |
| 38 | #define HOST_CTRL0_FSEL_MASK (7 << 16) |
| 39 | |
| 40 | #define EHCICTRL_ENAINCRXALIGN (1 << 29) |
| 41 | #define EHCICTRL_ENAINCR4 (1 << 28) |
| 42 | #define EHCICTRL_ENAINCR8 (1 << 27) |
| 43 | #define EHCICTRL_ENAINCR16 (1 << 26) |
| 44 | |
| 45 | /* Register map for PHY control */ |
| Rajeshwari Shinde | dad39d4 | 2012-05-21 16:38:03 +0530 | [diff] [blame] | 46 | struct exynos_usb_phy { |
| Rajeshwari Shinde | 9b4ae50 | 2012-05-02 19:18:51 +0530 | [diff] [blame] | 47 | unsigned int usbphyctrl0; |
| 48 | unsigned int usbphytune0; |
| 49 | unsigned int reserved1[2]; |
| 50 | unsigned int hsicphyctrl1; |
| 51 | unsigned int hsicphytune1; |
| 52 | unsigned int reserved2[2]; |
| 53 | unsigned int hsicphyctrl2; |
| 54 | unsigned int hsicphytune2; |
| 55 | unsigned int reserved3[2]; |
| 56 | unsigned int ehcictrl; |
| 57 | unsigned int ohcictrl; |
| 58 | unsigned int usbotgsys; |
| 59 | unsigned int reserved4; |
| 60 | unsigned int usbotgtune; |
| 61 | }; |
| 62 | |
| 63 | /* Switch on the VBUS power. */ |
| 64 | int board_usb_vbus_init(void); |
| 65 | |
| Rajeshwari Shinde | dad39d4 | 2012-05-21 16:38:03 +0530 | [diff] [blame] | 66 | #endif /* __ASM_ARM_ARCH_EHCI_H__ */ |