Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Chip-specific header file for the AT91SAM9x5 family |
| 3 | * |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 4 | * Copyright (C) 2012-2013 Atmel Corporation. |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 5 | * |
| 6 | * Definitions for the SoC: |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 7 | * AT91SAM9x5 & AT91SAM9N12 |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #ifndef __AT91SAM9X5_H__ |
| 16 | #define __AT91SAM9X5_H__ |
| 17 | |
| 18 | /* |
| 19 | * Peripheral identifiers/interrupts. |
| 20 | */ |
| 21 | #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
| 22 | #define ATMEL_ID_SYS 1 /* System Controller Interrupt */ |
| 23 | #define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */ |
| 24 | #define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */ |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 25 | #define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD), only for AT91SAM9X5 */ |
| 26 | #define ATMEL_ID_FUSE 4 /* FUSE Controller, only for AT91SAM9N12 */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 27 | #define ATMEL_ID_USART0 5 /* USART 0 */ |
| 28 | #define ATMEL_ID_USART1 6 /* USART 1 */ |
| 29 | #define ATMEL_ID_USART2 7 /* USART 2 */ |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 30 | #define ATMEL_ID_USART3 8 /* USART 3 */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 31 | #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */ |
| 32 | #define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */ |
| 33 | #define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */ |
| 34 | #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */ |
| 35 | #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */ |
| 36 | #define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */ |
| 37 | #define ATMEL_ID_UART0 15 /* UART 0 */ |
| 38 | #define ATMEL_ID_UART1 16 /* UART 1 */ |
| 39 | #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ |
| 40 | #define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */ |
| 41 | #define ATMEL_ID_ADC 19 /* ADC Controller */ |
| 42 | #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */ |
| 43 | #define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */ |
| 44 | #define ATMEL_ID_UHPHS 22 /* USB Host High Speed */ |
| 45 | #define ATMEL_ID_UDPHS 23 /* USB Device High Speed */ |
| 46 | #define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */ |
| 47 | #define ATMEL_ID_LCDC 25 /* LCD Controller */ |
| 48 | #define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */ |
| 49 | #define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */ |
| 50 | #define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */ |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 51 | #define ATMEL_ID_TRNG 30 /* True Random Number Generator */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 52 | #define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */ |
| 53 | |
| 54 | /* |
| 55 | * User Peripheral physical base addresses. |
| 56 | */ |
| 57 | #define ATMEL_BASE_SPI0 0xf0000000 |
| 58 | #define ATMEL_BASE_SPI1 0xf0004000 |
| 59 | #define ATMEL_BASE_HSMCI0 0xf0008000 |
| 60 | #define ATMEL_BASE_HSMCI1 0xf000c000 |
| 61 | #define ATMEL_BASE_SSC 0xf0010000 |
| 62 | #define ATMEL_BASE_CAN0 0xf8000000 |
| 63 | #define ATMEL_BASE_CAN1 0xf8004000 |
| 64 | #define ATMEL_BASE_TC0 0xf8008000 |
| 65 | #define ATMEL_BASE_TC1 0xf8008040 |
| 66 | #define ATMEL_BASE_TC2 0xf8008080 |
| 67 | #define ATMEL_BASE_TC3 0xf800c000 |
| 68 | #define ATMEL_BASE_TC4 0xf800c040 |
| 69 | #define ATMEL_BASE_TC5 0xf800c080 |
| 70 | #define ATMEL_BASE_TWI0 0xf8010000 |
| 71 | #define ATMEL_BASE_TWI1 0xf8014000 |
| 72 | #define ATMEL_BASE_TWI2 0xf8018000 |
| 73 | #define ATMEL_BASE_USART0 0xf801c000 |
| 74 | #define ATMEL_BASE_USART1 0xf8020000 |
| 75 | #define ATMEL_BASE_USART2 0xf8024000 |
| 76 | #define ATMEL_BASE_USART3 0xf8028000 |
| 77 | #define ATMEL_BASE_EMAC0 0xf802c000 |
| 78 | #define ATMEL_BASE_EMAC1 0xf8030000 |
| 79 | #define ATMEL_BASE_PWM 0xf8034000 |
| 80 | #define ATMEL_BASE_LCDC 0xf8038000 |
| 81 | #define ATMEL_BASE_UDPHS 0xf803c000 |
| 82 | #define ATMEL_BASE_UART0 0xf8040000 |
| 83 | #define ATMEL_BASE_UART1 0xf8044000 |
| 84 | #define ATMEL_BASE_ISI 0xf8048000 |
| 85 | #define ATMEL_BASE_ADC 0xf804c000 |
| 86 | #define ATMEL_BASE_SYS 0xffffc000 |
| 87 | |
| 88 | /* |
| 89 | * System Peripherals |
| 90 | */ |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 91 | #define ATMEL_BASE_FUSE 0xffffdc00 |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 92 | #define ATMEL_BASE_MATRIX 0xffffde00 |
| 93 | #define ATMEL_BASE_PMECC 0xffffe000 |
| 94 | #define ATMEL_BASE_PMERRLOC 0xffffe600 |
| 95 | #define ATMEL_BASE_DDRSDRC 0xffffe800 |
| 96 | #define ATMEL_BASE_SMC 0xffffea00 |
| 97 | #define ATMEL_BASE_DMAC0 0xffffec00 |
| 98 | #define ATMEL_BASE_DMAC1 0xffffee00 |
| 99 | #define ATMEL_BASE_AIC 0xfffff000 |
| 100 | #define ATMEL_BASE_DBGU 0xfffff200 |
| 101 | #define ATMEL_BASE_PIOA 0xfffff400 |
| 102 | #define ATMEL_BASE_PIOB 0xfffff600 |
| 103 | #define ATMEL_BASE_PIOC 0xfffff800 |
| 104 | #define ATMEL_BASE_PIOD 0xfffffa00 |
| 105 | #define ATMEL_BASE_PMC 0xfffffc00 |
| 106 | #define ATMEL_BASE_RSTC 0xfffffe00 |
| 107 | #define ATMEL_BASE_SHDWC 0xfffffe10 |
| 108 | #define ATMEL_BASE_PIT 0xfffffe30 |
| 109 | #define ATMEL_BASE_WDT 0xfffffe40 |
| 110 | #define ATMEL_BASE_GPBR 0xfffffe60 |
| 111 | #define ATMEL_BASE_RTC 0xfffffeb0 |
| 112 | |
| 113 | /* |
| 114 | * Internal Memory. |
| 115 | */ |
| 116 | #define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */ |
| 117 | #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 118 | |
| 119 | #ifdef CONFIG_AT91SAM9N12 |
| 120 | #define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller */ |
| 121 | #else /* AT91SAM9X5 */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 122 | #define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */ |
| 123 | #define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */ |
| 124 | #define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */ |
| 125 | #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */ |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 126 | #endif |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 127 | |
| 128 | /* 9x5 series chip id definitions */ |
| 129 | #define ARCH_ID_AT91SAM9X5 0x819a05a0 |
| 130 | #define ARCH_ID_VERSION_MASK 0x1f |
| 131 | #define ARCH_EXID_AT91SAM9G15 0x00000000 |
| 132 | #define ARCH_EXID_AT91SAM9G35 0x00000001 |
| 133 | #define ARCH_EXID_AT91SAM9X35 0x00000002 |
| 134 | #define ARCH_EXID_AT91SAM9G25 0x00000003 |
| 135 | #define ARCH_EXID_AT91SAM9X25 0x00000004 |
| 136 | |
| 137 | #define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5) |
| 138 | #define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \ |
| 139 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9G15)) |
| 140 | #define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \ |
| 141 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9G25)) |
| 142 | #define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \ |
| 143 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9G35)) |
| 144 | #define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \ |
| 145 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9X25)) |
| 146 | #define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \ |
| 147 | (get_extension_chip_id() == ARCH_EXID_AT91SAM9X35)) |
| 148 | |
| 149 | /* |
| 150 | * Cpu Name |
| 151 | */ |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 152 | #ifdef CONFIG_AT91SAM9N12 |
| 153 | #define ATMEL_CPU_NAME "AT91SAM9N12" |
| 154 | #else /* AT91SAM9X5 */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 155 | #define ATMEL_CPU_NAME get_cpu_name() |
Wu, Josh | 4320b45 | 2013-04-16 23:42:43 +0000 | [diff] [blame] | 156 | #endif |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 157 | |
| 158 | /* |
| 159 | * Other misc defines |
| 160 | */ |
| 161 | #define ATMEL_PIO_PORTS 4 |
| 162 | #define CPU_HAS_PIO3 |
| 163 | #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ |
Richard Genoud | b762a9c | 2012-11-29 23:18:32 +0000 | [diff] [blame] | 164 | #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP |
| 165 | #define ATMEL_ID_UHP ATMEL_ID_UHPHS |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 166 | |
| 167 | /* |
| 168 | * at91sam9x5 specific prototypes |
| 169 | */ |
| 170 | #ifndef __ASSEMBLY__ |
| 171 | unsigned int get_chip_id(void); |
| 172 | unsigned int get_extension_chip_id(void); |
| 173 | unsigned int has_emac1(void); |
| 174 | unsigned int has_emac0(void); |
| 175 | unsigned int has_lcdc(void); |
| 176 | char *get_cpu_name(void); |
| 177 | #endif |
| 178 | |
| 179 | #endif |