blob: f34a157902fc837acee71137eefbd9859895ac54 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Marek Vasut988ee702013-12-14 05:55:28 +01002/*
3 * Freescale i.MX6 PCI Express Root-Complex driver
4 *
5 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 *
7 * Based on upstream Linux kernel driver:
8 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
9 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
Marek Vasut988ee702013-12-14 05:55:28 +010010 */
11
12#include <common.h>
Simon Glass18afe102019-11-14 12:57:47 -070013#include <init.h>
Simon Glass9bc15642020-02-03 07:36:16 -070014#include <malloc.h>
Marek Vasut988ee702013-12-14 05:55:28 +010015#include <pci.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/iomux.h>
18#include <asm/arch/crm_regs.h>
Marek Vasutd9056c22014-02-03 21:46:22 +010019#include <asm/gpio.h>
Marek Vasut988ee702013-12-14 05:55:28 +010020#include <asm/io.h>
Marek Vasut3c9f33e2019-06-09 03:50:55 +020021#include <dm.h>
Alexey Brodkin267d8e22014-02-26 17:47:58 +040022#include <linux/sizes.h>
Marek Vasut988ee702013-12-14 05:55:28 +010023#include <errno.h>
Fabio Estevamb5272bd2015-10-13 11:01:27 -030024#include <asm/arch/sys_proto.h>
Marek Vasut988ee702013-12-14 05:55:28 +010025
26#define PCI_ACCESS_READ 0
27#define PCI_ACCESS_WRITE 1
28
Fabio Estevam211a4902014-08-25 14:26:45 -030029#ifdef CONFIG_MX6SX
30#define MX6_DBI_ADDR 0x08ffc000
31#define MX6_IO_ADDR 0x08000000
32#define MX6_MEM_ADDR 0x08100000
33#define MX6_ROOT_ADDR 0x08f00000
34#else
Marek Vasut988ee702013-12-14 05:55:28 +010035#define MX6_DBI_ADDR 0x01ffc000
Marek Vasut988ee702013-12-14 05:55:28 +010036#define MX6_IO_ADDR 0x01000000
Marek Vasut988ee702013-12-14 05:55:28 +010037#define MX6_MEM_ADDR 0x01100000
Marek Vasut988ee702013-12-14 05:55:28 +010038#define MX6_ROOT_ADDR 0x01f00000
Fabio Estevam211a4902014-08-25 14:26:45 -030039#endif
40#define MX6_DBI_SIZE 0x4000
41#define MX6_IO_SIZE 0x100000
42#define MX6_MEM_SIZE 0xe00000
Marek Vasut988ee702013-12-14 05:55:28 +010043#define MX6_ROOT_SIZE 0xfc000
44
45/* PCIe Port Logic registers (memory-mapped) */
46#define PL_OFFSET 0x700
Tim Harveyc22f2ea2017-05-12 12:58:41 -070047#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
48#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
49#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
Marek Vasut988ee702013-12-14 05:55:28 +010050#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
51#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
52#define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
53#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
54
55#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
56#define PCIE_PHY_CTRL_DATA_LOC 0
57#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
58#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
59#define PCIE_PHY_CTRL_WR_LOC 18
60#define PCIE_PHY_CTRL_RD_LOC 19
61
62#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
63#define PCIE_PHY_STAT_DATA_LOC 0
64#define PCIE_PHY_STAT_ACK_LOC 16
65
66/* PHY registers (not memory-mapped) */
67#define PCIE_PHY_RX_ASIC_OUT 0x100D
68
69#define PHY_RX_OVRD_IN_LO 0x1005
70#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
71#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
72
Fabio Estevam211a4902014-08-25 14:26:45 -030073#define PCIE_PHY_PUP_REQ (1 << 7)
74
Marek Vasut988ee702013-12-14 05:55:28 +010075/* iATU registers */
76#define PCIE_ATU_VIEWPORT 0x900
77#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
78#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
79#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
80#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
81#define PCIE_ATU_CR1 0x904
82#define PCIE_ATU_TYPE_MEM (0x0 << 0)
83#define PCIE_ATU_TYPE_IO (0x2 << 0)
84#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
85#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
86#define PCIE_ATU_CR2 0x908
87#define PCIE_ATU_ENABLE (0x1 << 31)
88#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
89#define PCIE_ATU_LOWER_BASE 0x90C
90#define PCIE_ATU_UPPER_BASE 0x910
91#define PCIE_ATU_LIMIT 0x914
92#define PCIE_ATU_LOWER_TARGET 0x918
93#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
94#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
95#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
96#define PCIE_ATU_UPPER_TARGET 0x91C
97
Marek Vasut6ce573f2019-06-09 03:50:52 +020098struct imx_pcie_priv {
99 void __iomem *dbi_base;
100 void __iomem *cfg_base;
101};
102
Marek Vasut988ee702013-12-14 05:55:28 +0100103/*
104 * PHY access functions
105 */
106static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
107{
108 u32 val;
109 u32 max_iterations = 10;
110 u32 wait_counter = 0;
111
112 do {
113 val = readl(dbi_base + PCIE_PHY_STAT);
114 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
115 wait_counter++;
116
117 if (val == exp_val)
118 return 0;
119
120 udelay(1);
121 } while (wait_counter < max_iterations);
122
123 return -ETIMEDOUT;
124}
125
126static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
127{
128 u32 val;
129 int ret;
130
131 val = addr << PCIE_PHY_CTRL_DATA_LOC;
132 writel(val, dbi_base + PCIE_PHY_CTRL);
133
134 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
135 writel(val, dbi_base + PCIE_PHY_CTRL);
136
137 ret = pcie_phy_poll_ack(dbi_base, 1);
138 if (ret)
139 return ret;
140
141 val = addr << PCIE_PHY_CTRL_DATA_LOC;
142 writel(val, dbi_base + PCIE_PHY_CTRL);
143
144 ret = pcie_phy_poll_ack(dbi_base, 0);
145 if (ret)
146 return ret;
147
148 return 0;
149}
150
151/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
152static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
153{
154 u32 val, phy_ctl;
155 int ret;
156
157 ret = pcie_phy_wait_ack(dbi_base, addr);
158 if (ret)
159 return ret;
160
161 /* assert Read signal */
162 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
163 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
164
165 ret = pcie_phy_poll_ack(dbi_base, 1);
166 if (ret)
167 return ret;
168
169 val = readl(dbi_base + PCIE_PHY_STAT);
170 *data = val & 0xffff;
171
172 /* deassert Read signal */
173 writel(0x00, dbi_base + PCIE_PHY_CTRL);
174
175 ret = pcie_phy_poll_ack(dbi_base, 0);
176 if (ret)
177 return ret;
178
179 return 0;
180}
181
182static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
183{
184 u32 var;
185 int ret;
186
187 /* write addr */
188 /* cap addr */
189 ret = pcie_phy_wait_ack(dbi_base, addr);
190 if (ret)
191 return ret;
192
193 var = data << PCIE_PHY_CTRL_DATA_LOC;
194 writel(var, dbi_base + PCIE_PHY_CTRL);
195
196 /* capture data */
197 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
198 writel(var, dbi_base + PCIE_PHY_CTRL);
199
200 ret = pcie_phy_poll_ack(dbi_base, 1);
201 if (ret)
202 return ret;
203
204 /* deassert cap data */
205 var = data << PCIE_PHY_CTRL_DATA_LOC;
206 writel(var, dbi_base + PCIE_PHY_CTRL);
207
208 /* wait for ack de-assertion */
209 ret = pcie_phy_poll_ack(dbi_base, 0);
210 if (ret)
211 return ret;
212
213 /* assert wr signal */
214 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
215 writel(var, dbi_base + PCIE_PHY_CTRL);
216
217 /* wait for ack */
218 ret = pcie_phy_poll_ack(dbi_base, 1);
219 if (ret)
220 return ret;
221
222 /* deassert wr signal */
223 var = data << PCIE_PHY_CTRL_DATA_LOC;
224 writel(var, dbi_base + PCIE_PHY_CTRL);
225
226 /* wait for ack de-assertion */
227 ret = pcie_phy_poll_ack(dbi_base, 0);
228 if (ret)
229 return ret;
230
231 writel(0x0, dbi_base + PCIE_PHY_CTRL);
232
233 return 0;
234}
235
Marek Vasut120efeb2019-06-09 03:50:54 +0200236static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
Marek Vasut988ee702013-12-14 05:55:28 +0100237{
238 u32 rc, ltssm;
239 int rx_valid, temp;
240
241 /* link is debug bit 36, debug register 1 starts at bit 32 */
Marek Vasut6ce573f2019-06-09 03:50:52 +0200242 rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
Marek Vasut988ee702013-12-14 05:55:28 +0100243 if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
244 !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
245 return -EAGAIN;
246
247 /*
248 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
249 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
250 * If (MAC/LTSSM.state == Recovery.RcvrLock)
251 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
252 * to gen2 is stuck
253 */
Marek Vasut6ce573f2019-06-09 03:50:52 +0200254 pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
255 ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
Marek Vasut988ee702013-12-14 05:55:28 +0100256
257 if (rx_valid & 0x01)
258 return 0;
259
260 if (ltssm != 0x0d)
261 return 0;
262
263 printf("transition to gen2 is stuck, reset PHY!\n");
264
Marek Vasut6ce573f2019-06-09 03:50:52 +0200265 pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
Marek Vasut988ee702013-12-14 05:55:28 +0100266 temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
Marek Vasut6ce573f2019-06-09 03:50:52 +0200267 pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
Marek Vasut988ee702013-12-14 05:55:28 +0100268
269 udelay(3000);
270
Marek Vasut6ce573f2019-06-09 03:50:52 +0200271 pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
Marek Vasut988ee702013-12-14 05:55:28 +0100272 temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
Marek Vasut6ce573f2019-06-09 03:50:52 +0200273 pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
Marek Vasut988ee702013-12-14 05:55:28 +0100274
275 return 0;
276}
277
278/*
279 * iATU region setup
280 */
Marek Vasut120efeb2019-06-09 03:50:54 +0200281static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
Marek Vasut988ee702013-12-14 05:55:28 +0100282{
283 /*
284 * i.MX6 defines 16MB in the AXI address map for PCIe.
285 *
286 * That address space excepted the pcie registers is
287 * split and defined into different regions by iATU,
288 * with sizes and offsets as follows:
289 *
290 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
291 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
292 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
293 */
294
295 /* CMD reg:I/O space, MEM space, and Bus Master Enable */
Marek Vasut6ce573f2019-06-09 03:50:52 +0200296 setbits_le32(priv->dbi_base + PCI_COMMAND,
Marek Vasut988ee702013-12-14 05:55:28 +0100297 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
298
299 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
Marek Vasut6ce573f2019-06-09 03:50:52 +0200300 setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
Marek Vasut988ee702013-12-14 05:55:28 +0100301 PCI_CLASS_BRIDGE_PCI << 16);
302
303 /* Region #0 is used for Outbound CFG space access. */
Marek Vasut6ce573f2019-06-09 03:50:52 +0200304 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
Marek Vasut988ee702013-12-14 05:55:28 +0100305
Marek Vasut2c20b752019-06-09 03:50:53 +0200306 writel(lower_32_bits((uintptr_t)priv->cfg_base),
307 priv->dbi_base + PCIE_ATU_LOWER_BASE);
308 writel(upper_32_bits((uintptr_t)priv->cfg_base),
309 priv->dbi_base + PCIE_ATU_UPPER_BASE);
310 writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
Marek Vasut6ce573f2019-06-09 03:50:52 +0200311 priv->dbi_base + PCIE_ATU_LIMIT);
Marek Vasut988ee702013-12-14 05:55:28 +0100312
Marek Vasut6ce573f2019-06-09 03:50:52 +0200313 writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
314 writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
315 writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
316 writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
Marek Vasut988ee702013-12-14 05:55:28 +0100317
318 return 0;
319}
320
321/*
322 * PCI Express accessors
323 */
Marek Vasut120efeb2019-06-09 03:50:54 +0200324static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
325 pci_dev_t d, int where)
Marek Vasut988ee702013-12-14 05:55:28 +0100326{
Marek Vasut2c20b752019-06-09 03:50:53 +0200327 void __iomem *va_address;
Marek Vasut988ee702013-12-14 05:55:28 +0100328
329 /* Reconfigure Region #0 */
Marek Vasut6ce573f2019-06-09 03:50:52 +0200330 writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
Marek Vasut988ee702013-12-14 05:55:28 +0100331
332 if (PCI_BUS(d) < 2)
Marek Vasut6ce573f2019-06-09 03:50:52 +0200333 writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
Marek Vasut988ee702013-12-14 05:55:28 +0100334 else
Marek Vasut6ce573f2019-06-09 03:50:52 +0200335 writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
Marek Vasut988ee702013-12-14 05:55:28 +0100336
337 if (PCI_BUS(d) == 0) {
Marek Vasut2c20b752019-06-09 03:50:53 +0200338 va_address = priv->dbi_base;
Marek Vasut988ee702013-12-14 05:55:28 +0100339 } else {
Marek Vasut6ce573f2019-06-09 03:50:52 +0200340 writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
Marek Vasut2c20b752019-06-09 03:50:53 +0200341 va_address = priv->cfg_base;
Marek Vasut988ee702013-12-14 05:55:28 +0100342 }
343
344 va_address += (where & ~0x3);
345
346 return va_address;
347}
348
349static int imx_pcie_addr_valid(pci_dev_t d)
350{
351 if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
352 return -EINVAL;
353 if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
354 return -EINVAL;
355 return 0;
356}
357
358/*
359 * Replace the original ARM DABT handler with a simple jump-back one.
360 *
361 * The problem here is that if we have a PCIe bridge attached to this PCIe
362 * controller, but no PCIe device is connected to the bridges' downstream
363 * port, the attempt to read/write from/to the config space will produce
364 * a DABT. This is a behavior of the controller and can not be disabled
365 * unfortuatelly.
366 *
367 * To work around the problem, we backup the current DABT handler address
368 * and replace it with our own DABT handler, which only bounces right back
369 * into the code.
370 */
371static void imx_pcie_fix_dabt_handler(bool set)
372{
373 extern uint32_t *_data_abort;
374 uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
375
376 static const uint32_t data_abort_bounce_handler = 0xe25ef004;
377 uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
378
379 static uint32_t data_abort_backup;
380
381 if (set) {
382 data_abort_backup = *data_abort_addr;
383 *data_abort_addr = data_abort_bounce_addr;
384 } else {
385 *data_abort_addr = data_abort_backup;
386 }
387}
388
Marek Vasut3c9f33e2019-06-09 03:50:55 +0200389static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
390 int where, u32 *val)
Marek Vasut988ee702013-12-14 05:55:28 +0100391{
Marek Vasut2c20b752019-06-09 03:50:53 +0200392 void __iomem *va_address;
Marek Vasut988ee702013-12-14 05:55:28 +0100393 int ret;
394
395 ret = imx_pcie_addr_valid(d);
396 if (ret) {
397 *val = 0xffffffff;
Bin Meng122c7662016-01-08 01:03:20 -0800398 return 0;
Marek Vasut988ee702013-12-14 05:55:28 +0100399 }
400
Marek Vasut120efeb2019-06-09 03:50:54 +0200401 va_address = get_bus_address(priv, d, where);
Marek Vasut988ee702013-12-14 05:55:28 +0100402
403 /*
404 * Read the PCIe config space. We must replace the DABT handler
405 * here in case we got data abort from the PCIe controller, see
406 * imx_pcie_fix_dabt_handler() description. Note that writing the
407 * "val" with valid value is also imperative here as in case we
408 * did got DABT, the val would contain random value.
409 */
410 imx_pcie_fix_dabt_handler(true);
411 writel(0xffffffff, val);
412 *val = readl(va_address);
413 imx_pcie_fix_dabt_handler(false);
414
415 return 0;
416}
417
Marek Vasut3c9f33e2019-06-09 03:50:55 +0200418static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
419 int where, u32 val)
Marek Vasut988ee702013-12-14 05:55:28 +0100420{
Marek Vasut2c20b752019-06-09 03:50:53 +0200421 void __iomem *va_address = NULL;
Marek Vasut988ee702013-12-14 05:55:28 +0100422 int ret;
423
424 ret = imx_pcie_addr_valid(d);
425 if (ret)
426 return ret;
427
Marek Vasut120efeb2019-06-09 03:50:54 +0200428 va_address = get_bus_address(priv, d, where);
Marek Vasut988ee702013-12-14 05:55:28 +0100429
430 /*
431 * Write the PCIe config space. We must replace the DABT handler
432 * here in case we got data abort from the PCIe controller, see
433 * imx_pcie_fix_dabt_handler() description.
434 */
435 imx_pcie_fix_dabt_handler(true);
436 writel(val, va_address);
437 imx_pcie_fix_dabt_handler(false);
438
439 return 0;
440}
441
442/*
443 * Initial bus setup
444 */
Marek Vasut120efeb2019-06-09 03:50:54 +0200445static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
446 bool prepare_for_boot)
Marek Vasut988ee702013-12-14 05:55:28 +0100447{
448 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
Fabio Estevamb5272bd2015-10-13 11:01:27 -0300449
450 if (is_mx6dqp())
451 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
452
Fabio Estevam211a4902014-08-25 14:26:45 -0300453#if defined(CONFIG_MX6SX)
454 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
Marek Vasut988ee702013-12-14 05:55:28 +0100455
Fabio Estevam211a4902014-08-25 14:26:45 -0300456 /* SSP_EN is not used on MX6SX anymore */
457 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
458 /* Force PCIe PHY reset */
459 setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
460 /* Power up PCIe PHY */
461 setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
462#else
Tim Harveyc22f2ea2017-05-12 12:58:41 -0700463 /*
464 * If the bootloader already enabled the link we need some special
465 * handling to get the core back into a state where it is safe to
466 * touch it for configuration. As there is no dedicated reset signal
467 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
468 * state before completely disabling LTSSM, which is a prerequisite
469 * for core configuration.
470 *
471 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
472 * indication that the bootloader activated the link.
473 */
Sven-Ola Tuecke5d679932017-10-05 08:46:42 -0300474 if (is_mx6dq() && prepare_for_boot) {
Tim Harveyc22f2ea2017-05-12 12:58:41 -0700475 u32 val, gpr1, gpr12;
476
477 gpr1 = readl(&iomuxc_regs->gpr[1]);
478 gpr12 = readl(&iomuxc_regs->gpr[12]);
479 if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
480 (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
Marek Vasut6ce573f2019-06-09 03:50:52 +0200481 val = readl(priv->dbi_base + PCIE_PL_PFLR);
Tim Harveyc22f2ea2017-05-12 12:58:41 -0700482 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
483 val |= PCIE_PL_PFLR_FORCE_LINK;
484
485 imx_pcie_fix_dabt_handler(true);
Marek Vasut6ce573f2019-06-09 03:50:52 +0200486 writel(val, priv->dbi_base + PCIE_PL_PFLR);
Tim Harveyc22f2ea2017-05-12 12:58:41 -0700487 imx_pcie_fix_dabt_handler(false);
488
489 gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
490 writel(val, &iomuxc_regs->gpr[12]);
491 }
492 }
Marek Vasut988ee702013-12-14 05:55:28 +0100493 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
494 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
Fabio Estevam211a4902014-08-25 14:26:45 -0300495#endif
Marek Vasut988ee702013-12-14 05:55:28 +0100496
497 return 0;
498}
499
500static int imx6_pcie_init_phy(void)
501{
502 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
503
504 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
505
506 clrsetbits_le32(&iomuxc_regs->gpr[12],
507 IOMUXC_GPR12_DEVICE_TYPE_MASK,
508 IOMUXC_GPR12_DEVICE_TYPE_RC);
509 clrsetbits_le32(&iomuxc_regs->gpr[12],
510 IOMUXC_GPR12_LOS_LEVEL_MASK,
511 IOMUXC_GPR12_LOS_LEVEL_9);
512
Fabio Estevam211a4902014-08-25 14:26:45 -0300513#ifdef CONFIG_MX6SX
514 clrsetbits_le32(&iomuxc_regs->gpr[12],
515 IOMUXC_GPR12_RX_EQ_MASK,
516 IOMUXC_GPR12_RX_EQ_2);
517#endif
518
Marek Vasut988ee702013-12-14 05:55:28 +0100519 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
520 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
521 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
522 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
523 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
524 &iomuxc_regs->gpr[8]);
525
526 return 0;
527}
528
Marek Vasut77779a42014-03-23 22:45:40 +0100529__weak int imx6_pcie_toggle_power(void)
530{
531#ifdef CONFIG_PCIE_IMX_POWER_GPIO
Peng Fan08e93382018-01-02 18:27:29 +0800532 gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
Marek Vasut77779a42014-03-23 22:45:40 +0100533 gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
534 mdelay(20);
535 gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
536 mdelay(20);
Peng Fan08e93382018-01-02 18:27:29 +0800537 gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
Marek Vasut77779a42014-03-23 22:45:40 +0100538#endif
539 return 0;
540}
541
Marek Vasutd9056c22014-02-03 21:46:22 +0100542__weak int imx6_pcie_toggle_reset(void)
543{
544 /*
545 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
546 * for detailed understanding of the PCIe CR reset logic.
547 *
548 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
549 * design does not conform to the specification. You must wait at
Fabio Estevam1d0b7e32015-09-10 20:45:25 -0300550 * least 20 ms after de-asserting the #PERST so the EP device can
Marek Vasutd9056c22014-02-03 21:46:22 +0100551 * do self-initialisation.
552 *
553 * In case your #PERST pin is connected to a plain GPIO pin of the
554 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
555 * configuration file and the condition below will handle the rest
556 * of the reset toggling.
557 *
558 * In case your #PERST toggling logic is more complex, for example
559 * connected via CPLD or somesuch, you can override this function
560 * in your board file and implement reset logic as needed. You must
Fabio Estevam1d0b7e32015-09-10 20:45:25 -0300561 * not forget to wait at least 20 ms after de-asserting #PERST in
Marek Vasutd9056c22014-02-03 21:46:22 +0100562 * this case either though.
563 *
564 * In case your #PERST line of the PCIe EP device is not connected
565 * at all, your design is broken and you should fix your design,
566 * otherwise you will observe problems like for example the link
567 * not coming up after rebooting the system back from running Linux
568 * that uses the PCIe as well OR the PCIe link might not come up in
569 * Linux at all in the first place since it's in some non-reset
570 * state due to being previously used in U-Boot.
571 */
572#ifdef CONFIG_PCIE_IMX_PERST_GPIO
Peng Fan08e93382018-01-02 18:27:29 +0800573 gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
Marek Vasutd9056c22014-02-03 21:46:22 +0100574 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
575 mdelay(20);
576 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
577 mdelay(20);
Peng Fan08e93382018-01-02 18:27:29 +0800578 gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
Marek Vasutd9056c22014-02-03 21:46:22 +0100579#else
580 puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
581#endif
582 return 0;
583}
584
Marek Vasut988ee702013-12-14 05:55:28 +0100585static int imx6_pcie_deassert_core_reset(void)
586{
587 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
588
Marek Vasut77779a42014-03-23 22:45:40 +0100589 imx6_pcie_toggle_power();
Marek Vasut988ee702013-12-14 05:55:28 +0100590
Marek Vasut988ee702013-12-14 05:55:28 +0100591 enable_pcie_clock();
592
Fabio Estevamb5272bd2015-10-13 11:01:27 -0300593 if (is_mx6dqp())
594 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
595
Marek Vasut988ee702013-12-14 05:55:28 +0100596 /*
597 * Wait for the clock to settle a bit, when the clock are sourced
Fabio Estevam1d0b7e32015-09-10 20:45:25 -0300598 * from the CPU, we need about 30 ms to settle.
Marek Vasut988ee702013-12-14 05:55:28 +0100599 */
Marek Vasutd9056c22014-02-03 21:46:22 +0100600 mdelay(50);
Marek Vasut988ee702013-12-14 05:55:28 +0100601
Fabio Estevam211a4902014-08-25 14:26:45 -0300602#if defined(CONFIG_MX6SX)
603 /* SSP_EN is not used on MX6SX anymore */
604 clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
605 /* Clear PCIe PHY reset bit */
606 clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
607#else
Tim Harveyd53204a2014-08-07 22:57:29 -0700608 /* Enable PCIe */
609 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
610 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
Fabio Estevam211a4902014-08-25 14:26:45 -0300611#endif
Tim Harveyd53204a2014-08-07 22:57:29 -0700612
Marek Vasutd9056c22014-02-03 21:46:22 +0100613 imx6_pcie_toggle_reset();
Marek Vasut988ee702013-12-14 05:55:28 +0100614
615 return 0;
616}
617
Marek Vasut120efeb2019-06-09 03:50:54 +0200618static int imx_pcie_link_up(struct imx_pcie_priv *priv)
Marek Vasut988ee702013-12-14 05:55:28 +0100619{
620 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
621 uint32_t tmp;
622 int count = 0;
623
Marek Vasut120efeb2019-06-09 03:50:54 +0200624 imx6_pcie_assert_core_reset(priv, false);
Marek Vasut988ee702013-12-14 05:55:28 +0100625 imx6_pcie_init_phy();
626 imx6_pcie_deassert_core_reset();
627
Marek Vasut120efeb2019-06-09 03:50:54 +0200628 imx_pcie_regions_setup(priv);
Marek Vasut988ee702013-12-14 05:55:28 +0100629
630 /*
Koen Vandeputte6be35052018-01-04 14:54:34 +0100631 * By default, the subordinate is set equally to the secondary
632 * bus (0x01) when the RC boots.
633 * This means that theoretically, only bus 1 is reachable from the RC.
634 * Force the PCIe RC subordinate to 0xff, otherwise no downstream
635 * devices will be detected if the enumeration is applied strictly.
636 */
Marek Vasut6ce573f2019-06-09 03:50:52 +0200637 tmp = readl(priv->dbi_base + 0x18);
Koen Vandeputte6be35052018-01-04 14:54:34 +0100638 tmp |= (0xff << 16);
Marek Vasut6ce573f2019-06-09 03:50:52 +0200639 writel(tmp, priv->dbi_base + 0x18);
Koen Vandeputte6be35052018-01-04 14:54:34 +0100640
641 /*
Marek Vasut988ee702013-12-14 05:55:28 +0100642 * FIXME: Force the PCIe RC to Gen1 operation
643 * The RC must be forced into Gen1 mode before bringing the link
644 * up, otherwise no downstream devices are detected. After the
645 * link is up, a managed Gen1->Gen2 transition can be initiated.
646 */
Marek Vasut6ce573f2019-06-09 03:50:52 +0200647 tmp = readl(priv->dbi_base + 0x7c);
Marek Vasut988ee702013-12-14 05:55:28 +0100648 tmp &= ~0xf;
649 tmp |= 0x1;
Marek Vasut6ce573f2019-06-09 03:50:52 +0200650 writel(tmp, priv->dbi_base + 0x7c);
Marek Vasut988ee702013-12-14 05:55:28 +0100651
652 /* LTSSM enable, starting link. */
653 setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
654
Marek Vasut120efeb2019-06-09 03:50:54 +0200655 while (!imx6_pcie_link_up(priv)) {
Marek Vasut988ee702013-12-14 05:55:28 +0100656 udelay(10);
657 count++;
Stefano Babicd1457922016-06-06 11:14:19 +0200658 if (count >= 4000) {
Tim Harveyc3260002015-05-08 15:17:10 -0700659#ifdef CONFIG_PCI_SCAN_SHOW
660 puts("PCI: pcie phy link never came up\n");
661#endif
Marek Vasut988ee702013-12-14 05:55:28 +0100662 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
Marek Vasut6ce573f2019-06-09 03:50:52 +0200663 readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
664 readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
Marek Vasut988ee702013-12-14 05:55:28 +0100665 return -EINVAL;
666 }
667 }
668
669 return 0;
670}
671
Marek Vasut3c9f33e2019-06-09 03:50:55 +0200672#if !CONFIG_IS_ENABLED(DM_PCI)
Marek Vasut120efeb2019-06-09 03:50:54 +0200673static struct imx_pcie_priv imx_pcie_priv = {
674 .dbi_base = (void __iomem *)MX6_DBI_ADDR,
675 .cfg_base = (void __iomem *)MX6_ROOT_ADDR,
676};
677
678static struct imx_pcie_priv *priv = &imx_pcie_priv;
679
Marek Vasut3c9f33e2019-06-09 03:50:55 +0200680static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
681 int where, u32 *val)
682{
683 struct imx_pcie_priv *priv = hose->priv_data;
684
685 return imx_pcie_read_cfg(priv, d, where, val);
686}
687
688static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
689 int where, u32 val)
690{
691 struct imx_pcie_priv *priv = hose->priv_data;
692
693 return imx_pcie_write_cfg(priv, d, where, val);
694}
695
Marek Vasut988ee702013-12-14 05:55:28 +0100696void imx_pcie_init(void)
697{
698 /* Static instance of the controller. */
699 static struct pci_controller pcc;
700 struct pci_controller *hose = &pcc;
701 int ret;
702
703 memset(&pcc, 0, sizeof(pcc));
704
Marek Vasut120efeb2019-06-09 03:50:54 +0200705 hose->priv_data = priv;
706
Marek Vasut988ee702013-12-14 05:55:28 +0100707 /* PCI I/O space */
708 pci_set_region(&hose->regions[0],
709 MX6_IO_ADDR, MX6_IO_ADDR,
710 MX6_IO_SIZE, PCI_REGION_IO);
711
712 /* PCI memory space */
713 pci_set_region(&hose->regions[1],
714 MX6_MEM_ADDR, MX6_MEM_ADDR,
715 MX6_MEM_SIZE, PCI_REGION_MEM);
716
717 /* System memory space */
718 pci_set_region(&hose->regions[2],
719 MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
720 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
721
722 hose->region_count = 3;
723
724 pci_set_ops(hose,
725 pci_hose_read_config_byte_via_dword,
726 pci_hose_read_config_word_via_dword,
727 imx_pcie_read_config,
728 pci_hose_write_config_byte_via_dword,
729 pci_hose_write_config_word_via_dword,
730 imx_pcie_write_config);
731
732 /* Start the controller. */
Marek Vasut120efeb2019-06-09 03:50:54 +0200733 ret = imx_pcie_link_up(priv);
Marek Vasut988ee702013-12-14 05:55:28 +0100734
735 if (!ret) {
736 pci_register_hose(hose);
737 hose->last_busno = pci_hose_scan(hose);
738 }
739}
740
Tim Harveyc22f2ea2017-05-12 12:58:41 -0700741void imx_pcie_remove(void)
742{
Marek Vasut120efeb2019-06-09 03:50:54 +0200743 imx6_pcie_assert_core_reset(priv, true);
Tim Harveyc22f2ea2017-05-12 12:58:41 -0700744}
745
Marek Vasut988ee702013-12-14 05:55:28 +0100746/* Probe function. */
747void pci_init_board(void)
748{
749 imx_pcie_init();
750}
Marek Vasut3c9f33e2019-06-09 03:50:55 +0200751#else
Simon Glass2a311e82020-01-27 08:49:37 -0700752static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
Marek Vasut3c9f33e2019-06-09 03:50:55 +0200753 uint offset, ulong *value,
754 enum pci_size_t size)
755{
756 struct imx_pcie_priv *priv = dev_get_priv(dev);
757 u32 tmpval;
758 int ret;
759
760 ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
761 if (ret)
762 return ret;
763
764 *value = pci_conv_32_to_size(tmpval, offset, size);
765 return 0;
766}
767
768static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
769 uint offset, ulong value,
770 enum pci_size_t size)
771{
772 struct imx_pcie_priv *priv = dev_get_priv(dev);
773 u32 tmpval, newval;
774 int ret;
775
776 ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
777 if (ret)
778 return ret;
779
780 newval = pci_conv_size_to_32(tmpval, value, offset, size);
781 return imx_pcie_write_cfg(priv, bdf, offset, newval);
782}
783
784static int imx_pcie_dm_probe(struct udevice *dev)
785{
786 struct imx_pcie_priv *priv = dev_get_priv(dev);
787
788 return imx_pcie_link_up(priv);
789}
790
791static int imx_pcie_dm_remove(struct udevice *dev)
792{
793 struct imx_pcie_priv *priv = dev_get_priv(dev);
794
795 imx6_pcie_assert_core_reset(priv, true);
796
797 return 0;
798}
799
800static int imx_pcie_ofdata_to_platdata(struct udevice *dev)
801{
802 struct imx_pcie_priv *priv = dev_get_priv(dev);
803
804 priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
805 priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
806 if (!priv->dbi_base || !priv->cfg_base)
807 return -EINVAL;
808
809 return 0;
810}
811
812static const struct dm_pci_ops imx_pcie_ops = {
813 .read_config = imx_pcie_dm_read_config,
814 .write_config = imx_pcie_dm_write_config,
815};
816
817static const struct udevice_id imx_pcie_ids[] = {
818 { .compatible = "fsl,imx6q-pcie" },
Marek Vasutbec7be12019-11-26 09:33:29 +0100819 { .compatible = "fsl,imx6sx-pcie" },
Marek Vasut3c9f33e2019-06-09 03:50:55 +0200820 { }
821};
822
823U_BOOT_DRIVER(imx_pcie) = {
824 .name = "imx_pcie",
825 .id = UCLASS_PCI,
826 .of_match = imx_pcie_ids,
827 .ops = &imx_pcie_ops,
828 .probe = imx_pcie_dm_probe,
829 .remove = imx_pcie_dm_remove,
830 .ofdata_to_platdata = imx_pcie_ofdata_to_platdata,
831 .priv_auto_alloc_size = sizeof(struct imx_pcie_priv),
832 .flags = DM_FLAG_OS_PREPARE,
833};
834#endif