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wdenked247f42002-10-07 21:58:02 +00001/*
2 * File: scc.c
3 * Description:
Wolfgang Denka1be4762008-05-20 16:00:29 +02004 * Basic ET HW initialization and packet RX/TX routines
wdenked247f42002-10-07 21:58:02 +00005 *
6 * NOTE <<<IMPORTANT: PLEASE READ>>>:
7 * Do not cache Rx/Tx buffers!
8 */
9
10/*
11 * MPC823 <-> MC68160 Connections:
12 *
13 * Setup MPC823 to work with MC68160 Enhanced Ethernet
14 * Serial Tranceiver as follows:
15 *
16 * MPC823 Signal MC68160 Comments
17 * ------ ------ ------- --------
18 * PA-12 ETHTX --------> TX Eth. Port Transmit Data
19 * PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
20 * PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
21 * PA-13 ETHRX <-------- RX Eth. Port Receive Data
22 * PC-8 E_RENA <-------- RENA Eth. Receive Enable
23 * PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
24 * PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
25 *
26 * FADS Board Signal MC68160 Comments
27 * ----------------- ------- --------
28 * (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
29 * (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
30 * (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
31 * (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
32 *
33 */
34
35#include <common.h>
36#include <malloc.h>
37#include <commproc.h>
38#include <net.h>
39#include <command.h>
40
Jon Loeliger526e5ce2007-07-09 19:06:00 -050041#if defined(CONFIG_CMD_NET) && defined(SCC_ENET)
wdenked247f42002-10-07 21:58:02 +000042
43/* Ethernet Transmit and Receive Buffers */
44#define DBUF_LENGTH 1520
45
46#define TX_BUF_CNT 2
47
wdenk6c59edc2004-05-03 20:45:30 +000048#define TOUT_LOOP 10000 /* 10 ms to have a packet sent */
wdenked247f42002-10-07 21:58:02 +000049
50static char txbuf[DBUF_LENGTH];
51
52static uint rxIdx; /* index of the current RX buffer */
53static uint txIdx; /* index of the current TX buffer */
54
55/*
56 * SCC Ethernet Tx and Rx buffer descriptors allocated at the
57 * immr->udata_bd address on Dual-Port RAM
58 * Provide for Double Buffering
59 */
60
61typedef volatile struct CommonBufferDescriptor {
62 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
63 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
64} RTXBD;
65
66static RTXBD *rtx;
67
Wolfgang Denkeba0fe32012-05-20 21:14:54 +000068static int scc_send(struct eth_device *dev, void *packet, int length);
wdenked247f42002-10-07 21:58:02 +000069static int scc_recv(struct eth_device* dev);
70static int scc_init (struct eth_device* dev, bd_t * bd);
71static void scc_halt(struct eth_device* dev);
72
73int scc_initialize(bd_t *bis)
74{
75 struct eth_device* dev;
76
77 dev = (struct eth_device*) malloc(sizeof *dev);
wdenk1272e232002-11-10 22:06:23 +000078 memset(dev, 0, sizeof *dev);
wdenked247f42002-10-07 21:58:02 +000079
Heiko Schocherc5e84052010-07-20 17:45:02 +020080 sprintf(dev->name, "SCC");
wdenked247f42002-10-07 21:58:02 +000081 dev->iobase = 0;
82 dev->priv = 0;
83 dev->init = scc_init;
84 dev->halt = scc_halt;
85 dev->send = scc_send;
86 dev->recv = scc_recv;
87
88 eth_register(dev);
89
90 return 1;
91}
92
Wolfgang Denkeba0fe32012-05-20 21:14:54 +000093static int scc_send(struct eth_device *dev, void *packet, int length)
wdenked247f42002-10-07 21:58:02 +000094{
95 int i, j=0;
96#if 0
97 volatile char *in, *out;
98#endif
99
100 /* section 16.9.23.3
101 * Wait for ready
102 */
103#if 0
104 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
105 out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
106 in = packet;
107 for(i = 0; i < length; i++) {
108 *out++ = *in++;
109 }
110 rtx->txbd[txIdx].cbd_datlen = length;
111 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
112 while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
113
114#ifdef ET_DEBUG
115 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
116#endif
117 i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
118
119 /* wrap around buffer index when necessary */
120 if (txIdx >= TX_BUF_CNT) txIdx = 0;
121#endif
122
123 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
124 udelay (1); /* will also trigger Wd if needed */
125 j++;
126 }
127 if (j>=TOUT_LOOP) printf("TX not ready\n");
128 rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
129 rtx->txbd[txIdx].cbd_datlen = length;
130 rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
131 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
132 udelay (1); /* will also trigger Wd if needed */
133 j++;
134 }
135 if (j>=TOUT_LOOP) printf("TX timeout\n");
136#ifdef ET_DEBUG
137 printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
138#endif
139 i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
140 return i;
141}
142
wdenk174e0e52003-12-07 22:27:15 +0000143static int scc_recv (struct eth_device *dev)
wdenked247f42002-10-07 21:58:02 +0000144{
145 int length;
146
wdenk174e0e52003-12-07 22:27:15 +0000147 for (;;) {
148 /* section 16.9.23.2 */
149 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
150 length = -1;
151 break; /* nothing received - leave for() loop */
152 }
wdenked247f42002-10-07 21:58:02 +0000153
wdenk174e0e52003-12-07 22:27:15 +0000154 length = rtx->rxbd[rxIdx].cbd_datlen;
wdenked247f42002-10-07 21:58:02 +0000155
wdenk174e0e52003-12-07 22:27:15 +0000156 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
wdenked247f42002-10-07 21:58:02 +0000157#ifdef ET_DEBUG
wdenk174e0e52003-12-07 22:27:15 +0000158 printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
wdenked247f42002-10-07 21:58:02 +0000159#endif
wdenk174e0e52003-12-07 22:27:15 +0000160 } else {
161 /* Pass the packet up to the protocol layers. */
162 NetReceive (NetRxPackets[rxIdx], length - 4);
163 }
wdenked247f42002-10-07 21:58:02 +0000164
165
wdenk174e0e52003-12-07 22:27:15 +0000166 /* Give the buffer back to the SCC. */
167 rtx->rxbd[rxIdx].cbd_datlen = 0;
wdenked247f42002-10-07 21:58:02 +0000168
wdenk174e0e52003-12-07 22:27:15 +0000169 /* wrap around buffer index when necessary */
170 if ((rxIdx + 1) >= PKTBUFSRX) {
171 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
172 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
173 rxIdx = 0;
174 } else {
175 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
176 rxIdx++;
177 }
wdenked247f42002-10-07 21:58:02 +0000178 }
wdenk174e0e52003-12-07 22:27:15 +0000179 return length;
wdenked247f42002-10-07 21:58:02 +0000180}
181
182/**************************************************************
183 *
184 * SCC Ethernet Initialization Routine
185 *
186 *************************************************************/
187
wdenk174e0e52003-12-07 22:27:15 +0000188static int scc_init (struct eth_device *dev, bd_t * bis)
wdenked247f42002-10-07 21:58:02 +0000189{
190
wdenk174e0e52003-12-07 22:27:15 +0000191 int i;
192 scc_enet_t *pram_ptr;
wdenked247f42002-10-07 21:58:02 +0000193
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenked247f42002-10-07 21:58:02 +0000195
wdenk174e0e52003-12-07 22:27:15 +0000196 pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
wdenked247f42002-10-07 21:58:02 +0000197
wdenk174e0e52003-12-07 22:27:15 +0000198 rxIdx = 0;
199 txIdx = 0;
wdenked247f42002-10-07 21:58:02 +0000200
Wolfgang Denkb824a1e2008-09-22 22:23:06 +0200201 if (!rtx) {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200202#ifdef CONFIG_SYS_ALLOC_DPRAM
Wolfgang Denkb824a1e2008-09-22 22:23:06 +0200203 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
204 dpram_alloc_align (sizeof (RTXBD), 8));
wdenked247f42002-10-07 21:58:02 +0000205#else
Wolfgang Denkb824a1e2008-09-22 22:23:06 +0200206 rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
207#endif
208 }
wdenked247f42002-10-07 21:58:02 +0000209
210#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
wdenk174e0e52003-12-07 22:27:15 +0000211 /* Configure port A pins for Txd and Rxd.
212 */
213 immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
214 immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
215 immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
wdenked247f42002-10-07 21:58:02 +0000216#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
wdenk174e0e52003-12-07 22:27:15 +0000217 /* Configure port B pins for Txd and Rxd.
218 */
219 immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
220 immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
221 immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
wdenked247f42002-10-07 21:58:02 +0000222#else
223#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
224#endif
225
226#if defined(PC_ENET_LBK)
wdenk174e0e52003-12-07 22:27:15 +0000227 /* Configure port C pins to disable External Loopback
228 */
229 immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
230 immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
231 immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
232 immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
233#endif /* PC_ENET_LBK */
wdenked247f42002-10-07 21:58:02 +0000234
wdenk174e0e52003-12-07 22:27:15 +0000235 /* Configure port C pins to enable CLSN and RENA.
236 */
237 immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
238 immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
239 immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
wdenked247f42002-10-07 21:58:02 +0000240
wdenk174e0e52003-12-07 22:27:15 +0000241 /* Configure port A for TCLK and RCLK.
242 */
243 immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
244 immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
wdenked247f42002-10-07 21:58:02 +0000245
wdenk174e0e52003-12-07 22:27:15 +0000246 /*
247 * Configure Serial Interface clock routing -- see section 16.7.5.3
248 * First, clear all SCC bits to zero, then set the ones we want.
249 */
wdenked247f42002-10-07 21:58:02 +0000250
wdenk174e0e52003-12-07 22:27:15 +0000251 immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
252 immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
wdenked247f42002-10-07 21:58:02 +0000253
254
wdenk174e0e52003-12-07 22:27:15 +0000255 /*
256 * Initialize SDCR -- see section 16.9.23.7
257 * SDMA configuration register
258 */
259 immr->im_siu_conf.sc_sdcr = 0x01;
wdenked247f42002-10-07 21:58:02 +0000260
261
wdenk174e0e52003-12-07 22:27:15 +0000262 /*
263 * Setup SCC Ethernet Parameter RAM
264 */
wdenked247f42002-10-07 21:58:02 +0000265
wdenk174e0e52003-12-07 22:27:15 +0000266 pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
267 pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
wdenked247f42002-10-07 21:58:02 +0000268
wdenk174e0e52003-12-07 22:27:15 +0000269 pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
wdenked247f42002-10-07 21:58:02 +0000270
wdenk174e0e52003-12-07 22:27:15 +0000271 pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
272 pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
wdenked247f42002-10-07 21:58:02 +0000273
wdenk174e0e52003-12-07 22:27:15 +0000274 /*
275 * Setup Receiver Buffer Descriptors (13.14.24.18)
276 * Settings:
277 * Empty, Wrap
278 */
wdenked247f42002-10-07 21:58:02 +0000279
wdenk174e0e52003-12-07 22:27:15 +0000280 for (i = 0; i < PKTBUFSRX; i++) {
281 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
282 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
283 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
284 }
wdenked247f42002-10-07 21:58:02 +0000285
wdenk174e0e52003-12-07 22:27:15 +0000286 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
wdenked247f42002-10-07 21:58:02 +0000287
wdenk174e0e52003-12-07 22:27:15 +0000288 /*
289 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
290 * Settings:
291 * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
292 */
wdenked247f42002-10-07 21:58:02 +0000293
wdenk174e0e52003-12-07 22:27:15 +0000294 for (i = 0; i < TX_BUF_CNT; i++) {
295 rtx->txbd[i].cbd_sc =
296 (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
297 rtx->txbd[i].cbd_datlen = 0; /* Reset */
298 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
299 }
wdenked247f42002-10-07 21:58:02 +0000300
wdenk174e0e52003-12-07 22:27:15 +0000301 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
wdenked247f42002-10-07 21:58:02 +0000302
wdenk174e0e52003-12-07 22:27:15 +0000303 /*
304 * Enter Command: Initialize Rx Params for SCC
305 */
wdenked247f42002-10-07 21:58:02 +0000306
wdenk174e0e52003-12-07 22:27:15 +0000307 do { /* Spin until ready to issue command */
308 __asm__ ("eieio");
309 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
310 /* Issue command */
311 immr->im_cpm.cp_cpcr =
312 ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
313 do { /* Spin until command processed */
314 __asm__ ("eieio");
315 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
wdenked247f42002-10-07 21:58:02 +0000316
wdenk174e0e52003-12-07 22:27:15 +0000317 /*
318 * Ethernet Specific Parameter RAM
319 * see table 13-16, pg. 660,
320 * pg. 681 (example with suggested settings)
321 */
wdenked247f42002-10-07 21:58:02 +0000322
wdenk174e0e52003-12-07 22:27:15 +0000323 pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
324 pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
325 pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
326 pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
327 pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
328 pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
wdenked247f42002-10-07 21:58:02 +0000329
wdenk174e0e52003-12-07 22:27:15 +0000330 pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
331 pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
332 pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
wdenked247f42002-10-07 21:58:02 +0000333
wdenk174e0e52003-12-07 22:27:15 +0000334 pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
335 pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
wdenked247f42002-10-07 21:58:02 +0000336
wdenk174e0e52003-12-07 22:27:15 +0000337 pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
338 pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
339 pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
340 pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
wdenked247f42002-10-07 21:58:02 +0000341
Joe Hershberger11cd5a02015-03-22 17:09:00 -0500342#define ea eth_get_ethaddr()
wdenk174e0e52003-12-07 22:27:15 +0000343 pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
344 pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
345 pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
wdenked247f42002-10-07 21:58:02 +0000346#undef ea
347
wdenk174e0e52003-12-07 22:27:15 +0000348 pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
349 pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
350 pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
351 pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
352 pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
353 pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
354 pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
355 pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
wdenked247f42002-10-07 21:58:02 +0000356
wdenk174e0e52003-12-07 22:27:15 +0000357 /*
358 * Enter Command: Initialize Tx Params for SCC
359 */
wdenked247f42002-10-07 21:58:02 +0000360
wdenk174e0e52003-12-07 22:27:15 +0000361 do { /* Spin until ready to issue command */
362 __asm__ ("eieio");
363 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
364 /* Issue command */
365 immr->im_cpm.cp_cpcr =
366 ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
367 do { /* Spin until command processed */
368 __asm__ ("eieio");
369 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
wdenked247f42002-10-07 21:58:02 +0000370
wdenk174e0e52003-12-07 22:27:15 +0000371 /*
372 * Mask all Events in SCCM - we use polling mode
373 */
374 immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
wdenked247f42002-10-07 21:58:02 +0000375
wdenk174e0e52003-12-07 22:27:15 +0000376 /*
377 * Clear Events in SCCE -- Clear bits by writing 1's
378 */
wdenked247f42002-10-07 21:58:02 +0000379
wdenk174e0e52003-12-07 22:27:15 +0000380 immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
wdenked247f42002-10-07 21:58:02 +0000381
382
wdenk174e0e52003-12-07 22:27:15 +0000383 /*
384 * Initialize GSMR High 32-Bits
385 * Settings: Normal Mode
386 */
wdenked247f42002-10-07 21:58:02 +0000387
wdenk174e0e52003-12-07 22:27:15 +0000388 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
wdenked247f42002-10-07 21:58:02 +0000389
wdenk174e0e52003-12-07 22:27:15 +0000390 /*
391 * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
392 * Settings:
393 * TCI = Invert
394 * TPL = 48 bits
395 * TPP = Repeating 10's
396 * MODE = Ethernet
397 */
wdenked247f42002-10-07 21:58:02 +0000398
wdenk174e0e52003-12-07 22:27:15 +0000399 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
400 SCC_GSMRL_TPL_48 |
401 SCC_GSMRL_TPP_10 |
402 SCC_GSMRL_MODE_ENET);
wdenked247f42002-10-07 21:58:02 +0000403
wdenk174e0e52003-12-07 22:27:15 +0000404 /*
405 * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
406 */
wdenked247f42002-10-07 21:58:02 +0000407
wdenk174e0e52003-12-07 22:27:15 +0000408 immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
wdenked247f42002-10-07 21:58:02 +0000409
wdenk174e0e52003-12-07 22:27:15 +0000410 /*
411 * Initialize the PSMR
412 * Settings:
413 * CRC = 32-Bit CCITT
414 * NIB = Begin searching for SFD 22 bits after RENA
415 * FDE = Full Duplex Enable
416 * LPB = Loopback Enable (Needed when FDE is set)
417 * BRO = Reject broadcast packets
418 * PROMISCOUS = Catch all packets regardless of dest. MAC adress
419 */
420 immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
421 SCC_PSMR_NIB22 |
wdenked247f42002-10-07 21:58:02 +0000422#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
wdenk174e0e52003-12-07 22:27:15 +0000423 SCC_PSMR_FDE | SCC_PSMR_LPB |
wdenked247f42002-10-07 21:58:02 +0000424#endif
425#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
wdenk174e0e52003-12-07 22:27:15 +0000426 SCC_PSMR_BRO |
wdenked247f42002-10-07 21:58:02 +0000427#endif
428#if defined(CONFIG_SCC_ENET_PROMISCOUS)
wdenk174e0e52003-12-07 22:27:15 +0000429 SCC_PSMR_PRO |
wdenked247f42002-10-07 21:58:02 +0000430#endif
wdenk174e0e52003-12-07 22:27:15 +0000431 0;
wdenked247f42002-10-07 21:58:02 +0000432
wdenk174e0e52003-12-07 22:27:15 +0000433 /*
434 * Configure Ethernet TENA Signal
435 */
wdenked247f42002-10-07 21:58:02 +0000436
437#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
wdenk174e0e52003-12-07 22:27:15 +0000438 immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
439 immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
wdenked247f42002-10-07 21:58:02 +0000440#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
wdenk174e0e52003-12-07 22:27:15 +0000441 immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
442 immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
wdenked247f42002-10-07 21:58:02 +0000443#else
444#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
445#endif
446
wdenk174e0e52003-12-07 22:27:15 +0000447 /*
448 * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
449 */
wdenked247f42002-10-07 21:58:02 +0000450
wdenk174e0e52003-12-07 22:27:15 +0000451 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
452 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
wdenked247f42002-10-07 21:58:02 +0000453
wdenk174e0e52003-12-07 22:27:15 +0000454 return 1;
wdenked247f42002-10-07 21:58:02 +0000455}
456
457
wdenk174e0e52003-12-07 22:27:15 +0000458static void scc_halt (struct eth_device *dev)
wdenked247f42002-10-07 21:58:02 +0000459{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200460 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk174e0e52003-12-07 22:27:15 +0000461
462 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
463 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
wdenk7ac16102004-08-01 22:48:16 +0000464
465 immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
wdenked247f42002-10-07 21:58:02 +0000466}
467
468#if 0
wdenk174e0e52003-12-07 22:27:15 +0000469void restart (void)
wdenked247f42002-10-07 21:58:02 +0000470{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200471 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk174e0e52003-12-07 22:27:15 +0000472
473 immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
474 (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
wdenked247f42002-10-07 21:58:02 +0000475}
476#endif
Jon Loeliger07efe2a2007-07-10 10:27:39 -0500477#endif