| Anup Patel | 83d5b50 | 2019-06-25 06:31:15 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* | ||||
| 3 | * Copyright (C) 2018-2019 SiFive, Inc. | ||||
| 4 | * Wesley Terpstra | ||||
| 5 | * Paul Walmsley | ||||
| 6 | */ | ||||
| 7 | |||||
| 8 | #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H | ||||
| 9 | #define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H | ||||
| 10 | |||||
| 11 | /* Clock indexes for use by Device Tree data and the PRCI driver */ | ||||
| 12 | |||||
| 13 | #define PRCI_CLK_COREPLL 0 | ||||
| 14 | #define PRCI_CLK_DDRPLL 1 | ||||
| 15 | #define PRCI_CLK_GEMGXLPLL 2 | ||||
| 16 | #define PRCI_CLK_TLCLK 3 | ||||
| 17 | |||||
| 18 | #endif | ||||