blob: 98d9753b7e34be14e9de5d0e792d161b6c409683 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Chris Zankel1387dab2016-08-10 18:36:44 +03002/*
3 * (C) Copyright 2008 - 2013 Tensilica Inc.
4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
Chris Zankel1387dab2016-08-10 18:36:44 +03005 */
6
7/*
8 * CPU specific code
9 */
10
11#include <common.h>
12#include <command.h>
Simon Glass97589732020-05-10 11:40:02 -060013#include <init.h>
Simon Glassf5c208d2019-11-14 12:57:20 -070014#include <vsprintf.h>
Chris Zankel1387dab2016-08-10 18:36:44 +030015#include <linux/stringify.h>
16#include <asm/global_data.h>
17#include <asm/cache.h>
18#include <asm/string.h>
19#include <asm/misc.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
Marek BehĂșn4bebdd32021-05-20 13:23:52 +020023gd_t *gd __section(".data");
Chris Zankel1387dab2016-08-10 18:36:44 +030024
25#if defined(CONFIG_DISPLAY_CPUINFO)
26/*
27 * Print information about the CPU.
28 */
29
30int print_cpuinfo(void)
31{
32 char buf[120], mhz[8];
33 uint32_t id0, id1;
34
35 asm volatile ("rsr %0, 176\n"
36 "rsr %1, 208\n"
37 : "=r"(id0), "=r"(id1));
38
39 sprintf(buf, "CPU: Xtensa %s (id: %08x:%08x) at %s MHz\n",
40 XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk));
41 puts(buf);
42 return 0;
43}
44#endif
45
46int arch_cpu_init(void)
47{
Tom Rinibb4dd962022-11-16 13:10:37 -050048 gd->ram_size = CFG_SYS_SDRAM_SIZE;
Chris Zankel1387dab2016-08-10 18:36:44 +030049 return 0;
50}
Simon Glassd35f3382017-04-06 12:47:05 -060051
52int dram_init(void)
53{
54 return 0;
55}