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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hans de Goededea16d22015-02-04 12:14:56 +01002/*
3 * DRAM init helper functions
4 *
5 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
Hans de Goededea16d22015-02-04 12:14:56 +01006 */
7
8#include <common.h>
Simon Glass495a5dc2019-11-14 12:57:30 -07009#include <time.h>
Andre Przywarae996bc62016-05-12 12:14:41 +010010#include <asm/barriers.h>
Hans de Goededea16d22015-02-04 12:14:56 +010011#include <asm/io.h>
12#include <asm/arch/dram.h>
13
14/*
15 * Wait up to 1s for value to be set in given part of reg.
16 */
17void mctl_await_completion(u32 *reg, u32 mask, u32 val)
18{
19 unsigned long tmo = timer_get_us() + 1000000;
20
21 while ((readl(reg) & mask) != val) {
22 if (timer_get_us() > tmo)
23 panic("Timeout initialising DRAM\n");
24 }
25}
26
27/*
28 * Test if memory at offset offset matches memory at begin of DRAM
Icenowy Zheng8701e102022-01-29 10:23:04 -050029 *
30 * Note: dsb() is not available on ARMv5 in Thumb mode
Hans de Goededea16d22015-02-04 12:14:56 +010031 */
Icenowy Zheng8701e102022-01-29 10:23:04 -050032#ifndef CONFIG_MACH_SUNIV
Hans de Goededea16d22015-02-04 12:14:56 +010033bool mctl_mem_matches(u32 offset)
34{
35 /* Try to write different values to RAM at two addresses */
Tom Rinibb4dd962022-11-16 13:10:37 -050036 writel(0, CFG_SYS_SDRAM_BASE);
37 writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset);
Tom Rini3b787ef2016-08-01 18:54:53 -040038 dsb();
Hans de Goededea16d22015-02-04 12:14:56 +010039 /* Check if the same value is actually observed when reading back */
Tom Rinibb4dd962022-11-16 13:10:37 -050040 return readl(CFG_SYS_SDRAM_BASE) ==
41 readl((ulong)CFG_SYS_SDRAM_BASE + offset);
Hans de Goededea16d22015-02-04 12:14:56 +010042}
Icenowy Zheng8701e102022-01-29 10:23:04 -050043#endif