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git01.mediatek.com / filogic / uboot / 11ad8cb431d2347d38ff08b3e659bb1212f1582e / . / configs / rock_defconfig
blob: 3ce9aa10670a934705a3440356a38b8704a761bb [file] [log] [blame]
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]1CONFIG_ARM=y
2# CONFIG_SPL_USE_ARCH_MEMCPY is not set
3# CONFIG_SPL_USE_ARCH_MEMSET is not set
4CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]5CONFIG_SYS_TEXT_BASE=0x60000000
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]6CONFIG_SYS_MALLOC_F_LEN=0x2000
7CONFIG_ROCKCHIP_RK3188=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]8CONFIG_TARGET_ROCK=y
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]9CONFIG_ENV_OFFSET=0x3F8000
Tom Rinic9285bf2019-04-29 15:54:04 -0400[diff] [blame]10CONFIG_SPL_STACK_R_ADDR=0x60080000
Tom Rinifdc7e362019-11-11 20:04:24 -0500[diff] [blame]11CONFIG_NR_DRAM_BANKS=1
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]12CONFIG_DEBUG_UART_BASE=0x20064000
13CONFIG_DEBUG_UART_CLOCK=24000000
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]14CONFIG_DEBUG_UART=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]15CONFIG_SPL_TEXT_BASE=0x10080800
Simon Glass4be229d2019-07-20 20:51:14 -0600[diff] [blame]16CONFIG_USE_PREBOOT=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]17CONFIG_DEFAULT_FDT_FILE="rk3188-radxarock.dtb"
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]18# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]19CONFIG_DISPLAY_BOARDINFO_LATE=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]20CONFIG_SPL_STACK_R=y
21CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Maxime Ripard24336442017-08-24 11:52:32 +0200[diff] [blame]22CONFIG_RANDOM_UUID=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]23CONFIG_CMD_I2C=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]24CONFIG_CMD_MMC=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]25CONFIG_CMD_SPI=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]26# CONFIG_CMD_SETEXPR is not set
27CONFIG_CMD_CACHE=y
28CONFIG_CMD_TIME=y
29CONFIG_CMD_REGULATOR=y
30CONFIG_SPL_OF_CONTROL=y
Tom Rini74060322018-09-03 15:26:12 -0400[diff] [blame]31CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]32CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
33CONFIG_SPL_OF_PLATDATA=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]34CONFIG_ENV_IS_IN_MMC=y
Tom Rinica63e712019-11-12 22:46:36 -0500[diff] [blame]35CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]36CONFIG_REGMAP=y
37CONFIG_SYSCON=y
38# CONFIG_SPL_SIMPLE_BUS is not set
39CONFIG_CLK=y
40CONFIG_ROCKCHIP_GPIO=y
41CONFIG_SYS_I2C_ROCKCHIP=y
42CONFIG_LED=y
43CONFIG_MMC_DW=y
44CONFIG_MMC_DW_ROCKCHIP=y
Patrick Delaunay0df81042019-02-27 15:20:36 +0100[diff] [blame]45CONFIG_SF_DEFAULT_SPEED=20000000
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]46CONFIG_PINCTRL=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]47CONFIG_DM_PMIC=y
48# CONFIG_SPL_PMIC_CHILDREN is not set
49CONFIG_PMIC_ACT8846=y
50CONFIG_REGULATOR_ACT8846=y
51CONFIG_DM_REGULATOR_FIXED=y
52CONFIG_RAM=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]53CONFIG_DEBUG_UART_SHIFT=2
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]54CONFIG_SYSRESET=y
Tom Rini2cbc1202018-04-28 10:45:55 -0400[diff] [blame]55CONFIG_TIMER=y
56CONFIG_SPL_TIMER=y
57CONFIG_ROCKCHIP_TIMER=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]58CONFIG_USB=y
59CONFIG_ROCKCHIP_USB2_PHY=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]60CONFIG_SPL_TINY_MEMSET=y
Heiko Stübnere1de6112017-03-26 21:09:55 +0200[diff] [blame]61CONFIG_CMD_DHRYSTONE=y
62CONFIG_ERRNO_STR=y