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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
haikunf6580d02015-03-25 20:23:26 +08002/*
Bin Meng4951af52016-01-13 19:39:05 -08003 * Freescale ls1021a TWR board common device tree source
haikunf6580d02015-03-25 20:23:26 +08004 *
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
haikunf6580d02015-03-25 20:23:26 +08006 */
7
haikunf6580d02015-03-25 20:23:26 +08008#include "ls1021a.dtsi"
Gaurav Jain119c7002022-06-23 16:31:35 +05309#include "ls1021a-twr-u-boot.dtsi"
haikunf6580d02015-03-25 20:23:26 +080010
11/ {
12 model = "LS1021A TWR Board";
13
14 aliases {
Rajesh Bhagat4d2cc552019-01-05 08:06:14 +000015 enet2-rgmii-phy = &rgmii_phy1;
16 enet0-sgmii-phy = &sgmii_phy2;
17 enet1-sgmii-phy = &sgmii_phy0;
Haikun.Wang@freescale.com07c851e2015-03-24 21:20:40 +080018 spi0 = &qspi;
Yuan Yaof9835162015-09-30 13:05:15 +053019 spi1 = &dspi1;
Haikun.Wang@freescale.com07c851e2015-03-24 21:20:40 +080020 };
Bin Meng06229a92016-01-13 19:38:59 -080021
22 chosen {
23 stdout-path = &uart0;
24 };
Haikun.Wang@freescale.com07c851e2015-03-24 21:20:40 +080025};
26
27&qspi {
Haikun.Wang@freescale.com07c851e2015-03-24 21:20:40 +080028 status = "okay";
29
Kuldeep Singh4c380872019-12-12 11:49:24 +053030 n25q128a130: flash@0 {
Haikun.Wang@freescale.com07c851e2015-03-24 21:20:40 +080031 #address-cells = <1>;
32 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +000033 compatible = "jedec,spi-nor";
Kuldeep Singh4c380872019-12-12 11:49:24 +053034 spi-max-frequency = <50000000>;
Haikun.Wang@freescale.com07c851e2015-03-24 21:20:40 +080035 reg = <0>;
haikunf6580d02015-03-25 20:23:26 +080036 };
37};
38
Yuan Yaof9835162015-09-30 13:05:15 +053039&dspi1 {
40 bus-num = <0>;
41 status = "okay";
42
43 dspiflash: at26df081a@0 {
44 #address-cells = <1>;
45 #size-cells = <1>;
Neil Armstronga009fa72019-02-10 10:16:20 +000046 compatible = "jedec,spi-nor";
Yuan Yaof9835162015-09-30 13:05:15 +053047 spi-max-frequency = <16000000>;
48 spi-cpol;
49 spi-cpha;
50 reg = <0>;
51 };
52};
53
Bin Meng19c04602019-07-19 00:29:59 +030054&enet0 {
55 tbi-handle = <&tbi0>;
56 phy-handle = <&sgmii_phy2>;
57 phy-connection-type = "sgmii";
58 status = "okay";
59};
60
61&enet1 {
62 tbi-handle = <&tbi1>;
63 phy-handle = <&sgmii_phy0>;
64 phy-connection-type = "sgmii";
65 status = "okay";
66};
67
68&enet2 {
69 phy-handle = <&rgmii_phy1>;
70 phy-connection-type = "rgmii-id";
71 status = "okay";
72};
73
haikunf6580d02015-03-25 20:23:26 +080074&i2c0 {
75 status = "okay";
76};
77
78&i2c1 {
79 status = "okay";
80};
81
82&ifc {
83 #address-cells = <2>;
84 #size-cells = <1>;
85 /* NOR Flash on board */
haikunb9fe9e22015-03-24 21:16:31 +080086 ranges = <0x0 0x0 0x60000000 0x08000000>;
haikunf6580d02015-03-25 20:23:26 +080087 status = "okay";
88
89 nor@0,0 {
90 #address-cells = <1>;
91 #size-cells = <1>;
92 compatible = "cfi-flash";
93 reg = <0x0 0x0 0x8000000>;
94 bank-width = <2>;
95 device-width = <1>;
96 };
97};
98
99&lpuart0 {
100 status = "okay";
101};
102
103&mdio0 {
104 sgmii_phy0: ethernet-phy@0 {
105 reg = <0x0>;
106 };
Bin Meng19c04602019-07-19 00:29:59 +0300107
haikunf6580d02015-03-25 20:23:26 +0800108 rgmii_phy1: ethernet-phy@1 {
109 reg = <0x1>;
110 };
Bin Meng19c04602019-07-19 00:29:59 +0300111
haikunf6580d02015-03-25 20:23:26 +0800112 sgmii_phy2: ethernet-phy@2 {
113 reg = <0x2>;
114 };
Bin Meng19c04602019-07-19 00:29:59 +0300115
116 /* SGMII PCS for enet0 */
117 tbi0: tbi-phy@1f {
118 reg = <0x1f>;
119 device_type = "tbi-phy";
120 };
121};
122
123&mdio1 {
124 /* SGMII PCS for enet1 */
haikunf6580d02015-03-25 20:23:26 +0800125 tbi1: tbi-phy@1f {
126 reg = <0x1f>;
127 device_type = "tbi-phy";
128 };
129};
130
131&uart0 {
132 status = "okay";
133};
134
135&uart1 {
136 status = "okay";
137};
Peng Ma739b3972018-08-01 14:15:41 +0800138
139&sata {
140 status = "okay";
141};