Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 1190a4e40ba9dd4741bb26c2eb7b14cf0d31a4b9 / . / arch / arm / dts / imx8mp-evk.dts
blob: 6df3beb92dc86c3d4bf4a5f069e48f29b9986522 [file] [log] [blame]
Peng Fanc47e09d2019-12-30 17:46:21 +0800[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mp.dtsi"
9
10/ {
11 model = "NXP i.MX8MPlus EVK board";
12 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
13
14 chosen {
15 stdout-path = &uart2;
16 };
17
18 memory@40000000 {
19 device_type = "memory";
20 reg = <0x0 0x40000000 0 0xc0000000>,
21 <0x1 0x00000000 0 0xc0000000>;
22 };
23
24 reg_usdhc2_vmmc: regulator-usdhc2 {
25 compatible = "regulator-fixed";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
28 regulator-name = "VSD_3V3";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
32 enable-active-high;
33 };
34};
35
36&fec {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_fec>;
39 phy-mode = "rgmii-id";
40 phy-handle = <&ethphy1>;
41 fsl,magic-packet;
42 status = "okay";
43
44 mdio {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 ethphy1: ethernet-phy@1 {
49 compatible = "ethernet-phy-ieee802.3-c22";
50 reg = <1>;
51 eee-broken-1000t;
52 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
53 };
54 };
55};
56
57&snvs_pwrkey {
58 status = "okay";
59};
60
61&uart2 {
62 /* console */
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_uart2>;
65 status = "okay";
66};
67
68&usdhc2 {
69 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
70 assigned-clock-rates = <400000000>;
71 pinctrl-names = "default", "state_100mhz", "state_200mhz";
72 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
73 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
74 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
75 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
76 vmmc-supply = <&reg_usdhc2_vmmc>;
77 bus-width = <4>;
78 status = "okay";
79};
80
81&usdhc3 {
82 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
83 assigned-clock-rates = <400000000>;
84 pinctrl-names = "default", "state_100mhz", "state_200mhz";
85 pinctrl-0 = <&pinctrl_usdhc3>;
86 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
87 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
88 bus-width = <8>;
89 non-removable;
90 status = "okay";
91};
92
93&wdog1 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_wdog>;
96 fsl,ext-reset-output;
97 status = "okay";
98};
99
100&iomuxc {
101 pinctrl-names = "default";
102
103 pinctrl_fec: fecgrp {
104 fsl,pins = <
105 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
106 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
107 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
108 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
109 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
110 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
111 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
112 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
113 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
114 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
115 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
116 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
117 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
118 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
119 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
120 >;
121 };
122
123 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
124 fsl,pins = <
125 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
126 >;
127 };
128
129 pinctrl_uart2: uart2grp {
130 fsl,pins = <
131 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
132 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
133 >;
134 };
135
136 pinctrl_usdhc2: usdhc2grp {
137 fsl,pins = <
138 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
139 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
140 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
141 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
142 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
143 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
144 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
145 >;
146 };
147
148 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
149 fsl,pins = <
150 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
151 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
152 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
153 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
154 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
155 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
156 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
157 >;
158 };
159
160 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
161 fsl,pins = <
162 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
163 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
164 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
165 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
166 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
167 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
168 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
169 >;
170 };
171
172 pinctrl_usdhc2_gpio: usdhc2grp-gpio {
173 fsl,pins = <
174 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
175 >;
176 };
177
178 pinctrl_usdhc3: usdhc3grp {
179 fsl,pins = <
180 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
181 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
182 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
183 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
184 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
185 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
186 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
187 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
188 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
189 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
190 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
191 >;
192 };
193
194 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
195 fsl,pins = <
196 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
197 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
198 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
199 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
200 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
201 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
202 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
203 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
204 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
205 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
206 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
207 >;
208 };
209
210 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
211 fsl,pins = <
212 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
213 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
214 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
215 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
216 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
217 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
218 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
219 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
220 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
221 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
222 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
223 >;
224 };
225
226 pinctrl_wdog: wdoggrp {
227 fsl,pins = <
228 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
229 >;
230 };
231};