Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | |
Patrice Chotard | 24dffa5 | 2019-02-19 16:49:05 +0100 | [diff] [blame] | 3 | #include <dt-bindings/memory/stm32-sdram.h> |
Patrice Chotard | cc4b0b0 | 2018-02-07 10:44:49 +0100 | [diff] [blame] | 4 | /{ |
| 5 | soc { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 6 | u-boot,dm-pre-reloc; |
| 7 | |
| 8 | fmc: fmc@A0000000 { |
| 9 | compatible = "st,stm32-fmc"; |
| 10 | reg = <0xA0000000 0x1000>; |
| 11 | clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>; |
| 12 | pinctrl-0 = <&fmc_pins>; |
| 13 | pinctrl-names = "default"; |
| 14 | status = "okay"; |
Patrice Chotard | cc4b0b0 | 2018-02-07 10:44:49 +0100 | [diff] [blame] | 15 | u-boot,dm-pre-reloc; |
| 16 | }; |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 17 | |
| 18 | mac: ethernet@40028000 { |
| 19 | compatible = "st,stm32-dwmac"; |
| 20 | reg = <0x40028000 0x8000>; |
| 21 | reg-names = "stmmaceth"; |
| 22 | clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>, |
| 23 | <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>, |
| 24 | <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>; |
| 25 | interrupts = <61>, <62>; |
| 26 | interrupt-names = "macirq", "eth_wake_irq"; |
| 27 | snps,pbl = <8>; |
| 28 | snps,mixed-burst; |
| 29 | dma-ranges; |
| 30 | pinctrl-0 = <ðernet_mii>; |
| 31 | phy-mode = "rmii"; |
| 32 | phy-handle = <&phy0>; |
| 33 | |
| 34 | status = "okay"; |
| 35 | |
| 36 | mdio0 { |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <0>; |
| 39 | compatible = "snps,dwmac-mdio"; |
| 40 | phy0: ethernet-phy@0 { |
| 41 | reg = <0>; |
| 42 | }; |
| 43 | }; |
| 44 | }; |
| 45 | |
| 46 | qspi: quadspi@A0001000 { |
| 47 | compatible = "st,stm32-qspi"; |
| 48 | #address-cells = <1>; |
| 49 | #size-cells = <0>; |
| 50 | reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>; |
| 51 | reg-names = "qspi", "qspi_mm"; |
| 52 | interrupts = <92>; |
| 53 | spi-max-frequency = <108000000>; |
| 54 | clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>; |
| 55 | resets = <&rcc STM32F7_AHB3_RESET(QSPI)>; |
| 56 | pinctrl-0 = <&qspi_pins>; |
| 57 | |
| 58 | status = "okay"; |
| 59 | }; |
Patrice Chotard | cc4b0b0 | 2018-02-07 10:44:49 +0100 | [diff] [blame] | 60 | }; |
| 61 | }; |
| 62 | |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 63 | &clk_hse { |
| 64 | u-boot,dm-pre-reloc; |
| 65 | }; |
| 66 | |
| 67 | &gpioa { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 68 | u-boot,dm-pre-reloc; |
| 69 | }; |
| 70 | |
| 71 | &gpiob { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 72 | u-boot,dm-pre-reloc; |
| 73 | }; |
| 74 | |
| 75 | &gpioc { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 76 | u-boot,dm-pre-reloc; |
| 77 | }; |
| 78 | |
| 79 | &gpiod { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 80 | u-boot,dm-pre-reloc; |
| 81 | }; |
| 82 | |
| 83 | &gpioe { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 84 | u-boot,dm-pre-reloc; |
| 85 | }; |
| 86 | |
| 87 | &gpiof { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 88 | u-boot,dm-pre-reloc; |
| 89 | }; |
| 90 | |
| 91 | &gpiog { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 92 | u-boot,dm-pre-reloc; |
| 93 | }; |
| 94 | |
| 95 | &gpioh { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 96 | u-boot,dm-pre-reloc; |
| 97 | }; |
| 98 | |
| 99 | &gpioi { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 100 | u-boot,dm-pre-reloc; |
| 101 | }; |
| 102 | |
Vikas Manocha | 3deae0d | 2017-04-12 14:16:36 -0700 | [diff] [blame] | 103 | &pinctrl { |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 104 | u-boot,dm-pre-reloc; |
| 105 | |
| 106 | fmc_pins: fmc@0 { |
| 107 | u-boot,dm-pre-reloc; |
| 108 | pins |
| 109 | { |
| 110 | u-boot,dm-pre-reloc; |
| 111 | }; |
| 112 | }; |
Vikas Manocha | 3deae0d | 2017-04-12 14:16:36 -0700 | [diff] [blame] | 113 | }; |
| 114 | |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 115 | &pwrcfg { |
| 116 | u-boot,dm-pre-reloc; |
Vikas Manocha | 3deae0d | 2017-04-12 14:16:36 -0700 | [diff] [blame] | 117 | }; |
Patrice Chotard | b957402 | 2017-11-15 13:14:43 +0100 | [diff] [blame] | 118 | |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 119 | &rcc { |
Patrice Chotard | b957402 | 2017-11-15 13:14:43 +0100 | [diff] [blame] | 120 | u-boot,dm-pre-reloc; |
| 121 | }; |
Patrice Chotard | a60d3f8 | 2018-01-18 13:39:29 +0100 | [diff] [blame] | 122 | |
Patrice Chotard | df2e02a | 2019-02-19 00:37:20 +0100 | [diff] [blame] | 123 | &timer5 { |
| 124 | u-boot,dm-pre-reloc; |
| 125 | }; |
| 126 | |
| 127 | &usart1 { |
Patrice Chotard | a60d3f8 | 2018-01-18 13:39:29 +0100 | [diff] [blame] | 128 | u-boot,dm-pre-reloc; |
Patrice Chotard | 555930a | 2019-02-18 23:19:45 +0100 | [diff] [blame] | 129 | clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>; |
Patrice Chotard | a60d3f8 | 2018-01-18 13:39:29 +0100 | [diff] [blame] | 130 | }; |