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Patrice Chotarddf2e02a2019-02-19 00:37:20 +01001// SPDX-License-Identifier: GPL-2.0+
2
Patrice Chotard24dffa52019-02-19 16:49:05 +01003#include <dt-bindings/memory/stm32-sdram.h>
Patrice Chotardcc4b0b02018-02-07 10:44:49 +01004/{
5 soc {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +01006 u-boot,dm-pre-reloc;
7
8 fmc: fmc@A0000000 {
9 compatible = "st,stm32-fmc";
10 reg = <0xA0000000 0x1000>;
11 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
12 pinctrl-0 = <&fmc_pins>;
13 pinctrl-names = "default";
14 status = "okay";
Patrice Chotardcc4b0b02018-02-07 10:44:49 +010015 u-boot,dm-pre-reloc;
16 };
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010017
18 mac: ethernet@40028000 {
19 compatible = "st,stm32-dwmac";
20 reg = <0x40028000 0x8000>;
21 reg-names = "stmmaceth";
22 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
23 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
24 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
25 interrupts = <61>, <62>;
26 interrupt-names = "macirq", "eth_wake_irq";
27 snps,pbl = <8>;
28 snps,mixed-burst;
29 dma-ranges;
30 pinctrl-0 = <&ethernet_mii>;
31 phy-mode = "rmii";
32 phy-handle = <&phy0>;
33
34 status = "okay";
35
36 mdio0 {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 compatible = "snps,dwmac-mdio";
40 phy0: ethernet-phy@0 {
41 reg = <0>;
42 };
43 };
44 };
45
46 qspi: quadspi@A0001000 {
47 compatible = "st,stm32-qspi";
48 #address-cells = <1>;
49 #size-cells = <0>;
50 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
51 reg-names = "qspi", "qspi_mm";
52 interrupts = <92>;
53 spi-max-frequency = <108000000>;
54 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
55 resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
56 pinctrl-0 = <&qspi_pins>;
57
58 status = "okay";
59 };
Patrice Chotardcc4b0b02018-02-07 10:44:49 +010060 };
61};
62
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010063&clk_hse {
64 u-boot,dm-pre-reloc;
65};
66
67&gpioa {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010068 u-boot,dm-pre-reloc;
69};
70
71&gpiob {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010072 u-boot,dm-pre-reloc;
73};
74
75&gpioc {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010076 u-boot,dm-pre-reloc;
77};
78
79&gpiod {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010080 u-boot,dm-pre-reloc;
81};
82
83&gpioe {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010084 u-boot,dm-pre-reloc;
85};
86
87&gpiof {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010088 u-boot,dm-pre-reloc;
89};
90
91&gpiog {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010092 u-boot,dm-pre-reloc;
93};
94
95&gpioh {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +010096 u-boot,dm-pre-reloc;
97};
98
99&gpioi {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100100 u-boot,dm-pre-reloc;
101};
102
Vikas Manocha3deae0d2017-04-12 14:16:36 -0700103&pinctrl {
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100104 u-boot,dm-pre-reloc;
105
106 fmc_pins: fmc@0 {
107 u-boot,dm-pre-reloc;
108 pins
109 {
110 u-boot,dm-pre-reloc;
111 };
112 };
Vikas Manocha3deae0d2017-04-12 14:16:36 -0700113};
114
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100115&pwrcfg {
116 u-boot,dm-pre-reloc;
Vikas Manocha3deae0d2017-04-12 14:16:36 -0700117};
Patrice Chotardb9574022017-11-15 13:14:43 +0100118
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100119&rcc {
Patrice Chotardb9574022017-11-15 13:14:43 +0100120 u-boot,dm-pre-reloc;
121};
Patrice Chotarda60d3f82018-01-18 13:39:29 +0100122
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100123&timer5 {
124 u-boot,dm-pre-reloc;
125};
126
127&usart1 {
Patrice Chotarda60d3f82018-01-18 13:39:29 +0100128 u-boot,dm-pre-reloc;
Patrice Chotard555930a2019-02-18 23:19:45 +0100129 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
Patrice Chotarda60d3f82018-01-18 13:39:29 +0100130};