Blame - arch/powerpc/include/asm/config.h - filogic/uboot

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Kumar Gala	4c88289	2009-02-05 20:40:57 -0600	[diff] [blame]	1	/*
Poonam Aggrwal	2ba3ee0	2011-01-13 21:39:27 +0530	[diff] [blame]	2	* Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala	4c88289	2009-02-05 20:40:57 -0600	[diff] [blame]	3	*
Wolfgang Denk	d79de1d	2013-07-08 09:37:19 +0200	[diff] [blame]	4	* SPDX-License-Identifier: GPL-2.0+
Kumar Gala	4c88289	2009-02-05 20:40:57 -0600	[diff] [blame]	5	*/
				6
				7	#ifndef _ASM_CONFIG_H_
				8	#define _ASM_CONFIG_H_
				9
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	10	#ifdef CONFIG_MPC85xx
				11	#include <asm/config_mpc85xx.h>
York Sun	f062659	2013-09-30 09:22:09 -0700	[diff] [blame]	12	#define CONFIG_SYS_FSL_DDR
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	13	#endif
				14
				15	#ifdef CONFIG_MPC86xx
				16	#include <asm/config_mpc86xx.h>
York Sun	f062659	2013-09-30 09:22:09 -0700	[diff] [blame]	17	#define CONFIG_SYS_FSL_DDR
				18	#endif
				19
				20	#ifdef CONFIG_MPC83xx
				21	#define CONFIG_SYS_FSL_DDR
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	22	#endif
				23
York Sun	e2cba15	2012-08-17 09:00:54 +0000	[diff] [blame]	24	#ifndef HWCONFIG_BUFFER_SIZE
				25	#define HWCONFIG_BUFFER_SIZE 256
				26	#endif
				27
Mingkai Hu	799efd9	2011-04-26 16:31:16 +0800	[diff] [blame]	28	/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
				29	#if defined(CONFIG_MPC8XXX_SPI) \|\| defined(CONFIG_FSL_ESPI)
				30	# ifndef CONFIG_HARD_SPI
				31	# define CONFIG_HARD_SPI
				32	# endif
				33	#endif
				34
Mike Frysinger	a0dadf8	2009-11-03 11:35:59 -0500	[diff] [blame]	35	#define CONFIG_LMB
John Rigby	eea8e69	2010-10-13 13:57:35 -0600	[diff] [blame]	36	#define CONFIG_SYS_BOOT_RAMDISK_HIGH
				37	#define CONFIG_SYS_BOOT_GET_CMDLINE
				38	#define CONFIG_SYS_BOOT_GET_KBD
Mike Frysinger	a0dadf8	2009-11-03 11:35:59 -0500	[diff] [blame]	39
Kumar Gala	4cd44a8	2009-02-05 20:40:58 -0600	[diff] [blame]	40	#ifndef CONFIG_MAX_MEM_MAPPED
York Sun	e12ce98	2011-08-26 11:32:44 -0700	[diff] [blame]	41	#if defined(CONFIG_4xx) \|\| \
				42	defined(CONFIG_E500) \|\| \
				43	defined(CONFIG_MPC86xx) \|\| \
				44	defined(CONFIG_E300)
Kumar Gala	4cd44a8	2009-02-05 20:40:58 -0600	[diff] [blame]	45	#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
				46	#else
Stefan Roese	a14295e	2009-02-11 09:37:12 +0100	[diff] [blame]	47	#define CONFIG_MAX_MEM_MAPPED (256 << 20)
Kumar Gala	4cd44a8	2009-02-05 20:40:58 -0600	[diff] [blame]	48	#endif
				49	#endif
				50
Peter Tyser	bee0168	2009-07-15 00:01:08 -0500	[diff] [blame]	51	/* Check if boards need to enable FSL DMA engine for SDRAM init */
				52	#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
				53	#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) \|\| \
				54	((defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx)) && \
				55	!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
Peter Tyser	ae7a7d4	2009-06-30 17:15:40 -0500	[diff] [blame]	56	#define CONFIG_FSL_DMA
				57	#endif
Kumar Gala	4c88289	2009-02-05 20:40:57 -0600	[diff] [blame]	58	#endif
Peter Tyser	ae7a7d4	2009-06-30 17:15:40 -0500	[diff] [blame]	59
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	60	#ifndef CONFIG_MAX_CPUS
Kumar Gala	bb5409c	2009-03-19 02:39:17 -0500	[diff] [blame]	61	#define CONFIG_MAX_CPUS 1
Poonam Aggrwal	4baef82	2009-07-31 12:08:14 +0530	[diff] [blame]	62	#endif
				63
Peter Tyser	7feaacb	2009-10-23 15:55:47 -0500	[diff] [blame]	64	/*
				65	* Provide a default boot page translation virtual address that lines up with
				66	* Freescale's default e500 reset page.
				67	*/
				68	#if (defined(CONFIG_E500) && defined(CONFIG_MP))
				69	#ifndef CONFIG_BPTR_VIRT_ADDR
				70	#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
				71	#endif
				72	#endif
				73
Kim Phillips	def125f	2010-06-01 12:24:27 -0500	[diff] [blame]	74	/*
				75	* SEC (crypto unit) major compatible version determination
				76	*/
Kumar Gala	fe13711	2011-01-19 03:05:26 -0600	[diff] [blame]	77	#if defined(CONFIG_MPC83xx)
Ruchika Gupta	272da15	2014-12-15 11:30:36 +0530	[diff] [blame]	78	#define CONFIG_SYS_FSL_SEC_BE
Kim Phillips	def125f	2010-06-01 12:24:27 -0500	[diff] [blame]	79	#define CONFIG_SYS_FSL_SEC_COMPAT 2
				80	#endif
				81
Becky Bruce	0d4cee1	2010-06-17 11:37:20 -0500	[diff] [blame]	82	/* Since so many PPC SOCs have a semi-common LBC, define this here */
				83	#if defined(CONFIG_MPC85xx) \|\| defined(CONFIG_MPC86xx) \|\| \
				84	defined(CONFIG_MPC83xx)
Dipen Dudhat	00c4294	2011-01-20 16:29:35 +0530	[diff] [blame]	85	#if !defined(CONFIG_FSL_IFC)
Becky Bruce	0d4cee1	2010-06-17 11:37:20 -0500	[diff] [blame]	86	#define CONFIG_FSL_LBC
				87	#endif
Dipen Dudhat	00c4294	2011-01-20 16:29:35 +0530	[diff] [blame]	88	#endif
Becky Bruce	0d4cee1	2010-06-17 11:37:20 -0500	[diff] [blame]	89
Andy Fleming	422effd	2011-04-08 02:10:54 -0500	[diff] [blame]	90	/* The TSEC driver uses the PHYLIB infrastructure */
				91	#ifndef CONFIG_PHYLIB
				92	#if defined(CONFIG_TSEC_ENET)
				93	#define CONFIG_PHYLIB
				94
				95	#include <config_phylib_all_drivers.h>
				96	#endif /* TSEC_ENET */
				97	#endif /* !CONFIG_PHYLIB */
				98
Kumar Gala	2683c53	2011-04-13 08:37:44 -0500	[diff] [blame]	99	/* The FMAN driver uses the PHYLIB infrastructure */
				100	#if defined(CONFIG_FMAN_ENET)
				101	#define CONFIG_PHYLIB
				102	#endif
				103
Albert Aribaud	036c6b4	2010-08-08 05:17:05 +0530	[diff] [blame]	104	/* All PPC boards must swap IDE bytes */
				105	#define CONFIG_IDE_SWAP_IO
				106
Thomas Chou	78b9881	2015-11-19 21:48:07 +0800	[diff] [blame]	107	#if defined(CONFIG_DM_SERIAL)
				108	/*
				109	* TODO: Convert this to a clock driver exists that can give us the UART
				110	* clock here.
				111	*/
				112	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
				113	#endif
				114
Peter Tyser	ae7a7d4	2009-06-30 17:15:40 -0500	[diff] [blame]	115	#endif /* _ASM_CONFIG_H_ */