blob: fefb568f7aef7e4cfca99628f01a18e9a960d8f1 [file] [log] [blame]
huang lin5aaa2872015-11-17 14:20:18 +08001/*
2 * (C) Copyright 2015 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
10#include <reset.h>
11#include <asm/io.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/cru_rk3036.h>
14#include <asm/arch/hardware.h>
15#include <linux/err.h>
16
17int rk3036_reset_request(struct udevice *dev, enum reset_t type)
18{
19 struct rk3036_cru *cru = rockchip_get_cru();
20
21 if (IS_ERR(cru))
22 return PTR_ERR(cru);
23 switch (type) {
24 case RESET_WARM:
25 writel(0xeca8, &cru->cru_glb_srst_snd_value);
26 break;
27 case RESET_COLD:
28 writel(0xfdb9, &cru->cru_glb_srst_fst_value);
29 break;
30 default:
31 return -EPROTONOSUPPORT;
32 }
33
34 return -EINPROGRESS;
35}
36
37static struct reset_ops rk3036_reset = {
38 .request = rk3036_reset_request,
39};
40
41U_BOOT_DRIVER(reset_rk3036) = {
42 .name = "rk3036_reset",
43 .id = UCLASS_RESET,
44 .ops = &rk3036_reset,
45};