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Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare ABP UART
8
9maintainers:
10 - Rob Herring <robh@kernel.org>
11
12allOf:
13 - $ref: serial.yaml#
Tom Rini93743d22024-04-01 09:08:13 -040014 - $ref: rs485.yaml#
Tom Rini53633a82024-02-29 12:33:36 -050015
Tom Rini6b642ac2024-10-01 12:20:28 -060016 - if:
17 properties:
18 compatible:
19 contains:
20 const: starfive,jh7110-uart
21 then:
22 properties:
23 resets:
24 minItems: 2
25 else:
26 properties:
27 resets:
28 maxItems: 1
29
Tom Rini53633a82024-02-29 12:33:36 -050030properties:
31 compatible:
32 oneOf:
33 - items:
34 - enum:
35 - renesas,r9a06g032-uart
36 - renesas,r9a06g033-uart
37 - const: renesas,rzn1-uart
38 - items:
39 - enum:
40 - rockchip,px30-uart
41 - rockchip,rk1808-uart
42 - rockchip,rk3036-uart
43 - rockchip,rk3066-uart
44 - rockchip,rk3128-uart
45 - rockchip,rk3188-uart
46 - rockchip,rk3288-uart
47 - rockchip,rk3308-uart
48 - rockchip,rk3328-uart
49 - rockchip,rk3368-uart
50 - rockchip,rk3399-uart
51 - rockchip,rk3568-uart
52 - rockchip,rk3588-uart
53 - rockchip,rv1108-uart
54 - rockchip,rv1126-uart
55 - const: snps,dw-apb-uart
56 - items:
57 - enum:
58 - brcm,bcm11351-dw-apb-uart
59 - brcm,bcm21664-dw-apb-uart
60 - const: snps,dw-apb-uart
61 - items:
62 - enum:
63 - starfive,jh7100-hsuart
64 - starfive,jh7100-uart
Tom Rini6b642ac2024-10-01 12:20:28 -060065 - starfive,jh7110-uart
Tom Rini53633a82024-02-29 12:33:36 -050066 - const: snps,dw-apb-uart
67 - const: snps,dw-apb-uart
68
69 reg:
70 maxItems: 1
71
72 interrupts:
73 maxItems: 1
74
75 clock-frequency: true
76
77 clocks:
78 minItems: 1
79 maxItems: 2
80
81 clock-names:
82 items:
83 - const: baudclk
84 - const: apb_pclk
85
86 dmas:
87 maxItems: 2
88
89 dma-names:
90 items:
91 - const: tx
92 - const: rx
93
94 snps,uart-16550-compatible:
95 description: reflects the value of UART_16550_COMPATIBLE configuration
96 parameter. Define this if your UART does not implement the busy functionality.
97 type: boolean
98
99 resets:
Tom Rini6b642ac2024-10-01 12:20:28 -0600100 minItems: 1
101 maxItems: 2
Tom Rini53633a82024-02-29 12:33:36 -0500102
103 reg-shift: true
104
105 reg-io-width: true
106
107 dcd-override:
108 description: Override the DCD modem status signal. This signal will
109 always be reported as active instead of being obtained from the modem
110 status register. Define this if your serial port does not use this
111 pin.
112 type: boolean
113
114 dsr-override:
115 description: Override the DTS modem status signal. This signal will
116 always be reported as active instead of being obtained from the modem
117 status register. Define this if your serial port does not use this
118 pin.
119 type: boolean
120
121 cts-override:
122 description: Override the CTS modem status signal. This signal will
123 always be reported as active instead of being obtained from the modem
124 status register. Define this if your serial port does not use this
125 pin.
126 type: boolean
127
128 ri-override:
129 description: Override the RI modem status signal. This signal will always
130 be reported as inactive instead of being obtained from the modem status
131 register. Define this if your serial port does not use this pin.
132 type: boolean
133
134required:
135 - compatible
136 - reg
137
138unevaluatedProperties: false
139
140examples:
141 - |
142 serial@80230000 {
143 compatible = "snps,dw-apb-uart";
144 reg = <0x80230000 0x100>;
145 clock-frequency = <3686400>;
146 interrupts = <10>;
147 reg-shift = <2>;
148 reg-io-width = <4>;
149 dcd-override;
150 dsr-override;
151 cts-override;
152 ri-override;
153 };
154
155 - |
156 // Example with one clock:
157 serial@80230000 {
158 compatible = "snps,dw-apb-uart";
159 reg = <0x80230000 0x100>;
160 clocks = <&baudclk>;
161 interrupts = <10>;
162 reg-shift = <2>;
163 reg-io-width = <4>;
164 };
165
166 - |
167 // Example with two clocks:
168 serial@80230000 {
169 compatible = "snps,dw-apb-uart";
170 reg = <0x80230000 0x100>;
171 clocks = <&baudclk>, <&apb_pclk>;
172 clock-names = "baudclk", "apb_pclk";
173 interrupts = <10>;
174 reg-shift = <2>;
175 reg-io-width = <4>;
176 };
177...