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git01.mediatek.com / filogic / uboot / 1112b4e509c5772610ad19a3ea399afd667c46a5 / . / arch / arm / dts / imx6qdl-gw5910.dtsi
blob: 56d0c4ff6c8592eebbdc30f0755c34f7f856b2e6 [file] [log] [blame]
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2019 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
16 };
17
18 chosen {
19 stdout-path = &uart2;
20 };
21
22 memory@10000000 {
23 device_type = "memory";
24 reg = <0x10000000 0x20000000>;
25 };
26
27 gpio-keys {
28 compatible = "gpio-keys";
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 user-pb {
33 label = "user_pb";
34 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
35 linux,code = <BTN_0>;
36 };
37
38 user-pb1x {
39 label = "user_pb1x";
40 linux,code = <BTN_1>;
41 interrupt-parent = <&gsc>;
42 interrupts = <0>;
43 };
44
45 key-erased {
46 label = "key-erased";
47 linux,code = <BTN_2>;
48 interrupt-parent = <&gsc>;
49 interrupts = <1>;
50 };
51
52 eeprom-wp {
53 label = "eeprom_wp";
54 linux,code = <BTN_3>;
55 interrupt-parent = <&gsc>;
56 interrupts = <2>;
57 };
58
59 tamper {
60 label = "tamper";
61 linux,code = <BTN_4>;
62 interrupt-parent = <&gsc>;
63 interrupts = <5>;
64 };
65
66 switch-hold {
67 label = "switch_hold";
68 linux,code = <BTN_5>;
69 interrupt-parent = <&gsc>;
70 interrupts = <7>;
71 };
72 };
73
74 leds {
75 compatible = "gpio-leds";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_gpio_leds>;
78
79 led0: user1 {
80 label = "user1";
81 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
82 default-state = "on";
83 linux,default-trigger = "heartbeat";
84 };
85
86 led1: user2 {
87 label = "user2";
88 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
89 default-state = "off";
90 };
91
92 led2: user3 {
93 label = "user3";
94 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
95 default-state = "off";
96 };
97 };
98
99 pps {
100 compatible = "pps-gpio";
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_pps>;
103 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
104 status = "okay";
105 };
106
107 reg_3p3v: regulator-3p3v {
108 compatible = "regulator-fixed";
109 regulator-name = "3P3V";
110 regulator-min-microvolt = <3300000>;
111 regulator-max-microvolt = <3300000>;
112 regulator-always-on;
113 };
114
115 reg_5p0v: regulator-5p0v {
116 compatible = "regulator-fixed";
117 regulator-name = "5P0V";
118 regulator-min-microvolt = <5000000>;
119 regulator-max-microvolt = <5000000>;
120 regulator-always-on;
121 };
122
123 reg_wl: regulator-wl {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_reg_wl>;
126 compatible = "regulator-fixed";
127 regulator-name = "wl";
128 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
129 startup-delay-us = <100>;
130 enable-active-high;
131 regulator-min-microvolt = <3300000>;
132 regulator-max-microvolt = <3300000>;
133 };
134};
135
136
137&ecspi3 {
138 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_ecspi3>;
141 status = "okay";
142};
143
144&fec {
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_enet>;
147 phy-mode = "rgmii-id";
148 status = "okay";
149};
150
151&gpmi {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_gpmi_nand>;
154 status = "okay";
155};
156
157&i2c1 {
158 clock-frequency = <100000>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_i2c1>;
161 status = "okay";
162
163 gsc: gsc@20 {
164 compatible = "gw,gsc";
165 reg = <0x20>;
166 interrupt-parent = <&gpio1>;
167 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
168 interrupt-controller;
169 #interrupt-cells = <1>;
170 #size-cells = <0>;
171
172 adc {
173 compatible = "gw,gsc-adc";
174 #address-cells = <1>;
175 #size-cells = <0>;
176
177 channel@6 {
178 gw,mode = <0>;
179 reg = <0x06>;
180 label = "temp";
181 };
182
183 channel@8 {
184 gw,mode = <3>;
185 reg = <0x08>;
186 label = "vdd_bat";
187 };
188
189 channel@82 {
190 gw,mode = <2>;
191 reg = <0x82>;
192 label = "vdd_vin";
193 gw,voltage-divider-ohms = <22100 1000>;
194 gw,voltage-offset-microvolt = <800000>;
195 };
196
197 channel@84 {
198 gw,mode = <2>;
199 reg = <0x84>;
200 label = "vdd_5p0";
201 gw,voltage-divider-ohms = <22100 10000>;
202 };
203
204 channel@86 {
205 gw,mode = <2>;
206 reg = <0x86>;
207 label = "vdd_3p3";
208 gw,voltage-divider-ohms = <10000 10000>;
209 };
210
211 channel@88 {
212 gw,mode = <2>;
213 reg = <0x88>;
214 label = "vdd_2p5";
215 gw,voltage-divider-ohms = <10000 10000>;
216 };
217
218 channel@8c {
219 gw,mode = <2>;
220 reg = <0x8c>;
221 label = "vdd_3p0";
222 };
223
224 channel@8e {
225 gw,mode = <2>;
226 reg = <0x8e>;
227 label = "vdd_arm";
228 };
229
230 channel@90 {
231 gw,mode = <2>;
232 reg = <0x90>;
233 label = "vdd_soc";
234 };
235
236 channel@92 {
237 gw,mode = <2>;
238 reg = <0x92>;
239 label = "vdd_1p5";
240 };
241
242 channel@98 {
243 gw,mode = <2>;
244 reg = <0x98>;
245 label = "vdd_1p8";
246 };
247
248 channel@9a {
249 gw,mode = <2>;
250 reg = <0x9a>;
251 label = "vdd_1p0";
252 gw,voltage-divider-ohms = <10000 10000>;
253 };
254
255 channel@9c {
256 gw,mode = <2>;
257 reg = <0x9c>;
258 label = "vdd_an1";
259 gw,voltage-divider-ohms = <10000 10000>;
260 };
261
262 channel@a2 {
263 gw,mode = <2>;
264 reg = <0xa2>;
265 label = "vdd_gsc";
266 gw,voltage-divider-ohms = <10000 10000>;
267 };
268 };
269 };
270
271 gsc_gpio: gpio@23 {
272 compatible = "nxp,pca9555";
273 reg = <0x23>;
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-parent = <&gsc>;
277 interrupts = <4>;
278 };
279
280 eeprom@50 {
281 compatible = "atmel,24c02";
282 reg = <0x50>;
283 pagesize = <16>;
284 };
285
286 eeprom@51 {
287 compatible = "atmel,24c02";
288 reg = <0x51>;
289 pagesize = <16>;
290 };
291
292 eeprom@52 {
293 compatible = "atmel,24c02";
294 reg = <0x52>;
295 pagesize = <16>;
296 };
297
298 eeprom@53 {
299 compatible = "atmel,24c02";
300 reg = <0x53>;
301 pagesize = <16>;
302 };
303
304 rtc@68 {
305 compatible = "dallas,ds1672";
306 reg = <0x68>;
307 };
308};
309
310&i2c2 {
311 clock-frequency = <100000>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_i2c2>;
314 status = "okay";
315};
316
317&i2c3 {
318 clock-frequency = <100000>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_i2c3>;
321 status = "okay";
322
323 accel@19 {
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_accel>;
326 compatible = "st,lis2de12";
327 reg = <0x19>;
328 st,drdy-int-pin = <1>;
329 interrupt-parent = <&gpio7>;
330 interrupts = <13 0>;
331 interrupt-names = "INT1";
332 };
333};
334
335&pcie {
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_pcie>;
338 reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
339 status = "okay";
340};
341
342&pwm2 {
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
345 status = "disabled";
346};
347
348&pwm3 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
351 status = "disabled";
352};
353
354/* off-board RS232 */
355&uart1 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_uart1>;
358 status = "okay";
359};
360
361/* serial console */
362&uart2 {
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_uart2>;
365 status = "okay";
366};
367
368/* cc1352 */
369&uart3 {
370 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_uart3>;
372 uart-has-rtscts;
373 status = "okay";
374};
375
376/* Sterling-LWB Bluetooth */
377&uart4 {
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
380 uart-has-rtscts;
381 status = "okay";
382
383 bluetooth {
384 compatible = "brcm,bcm4330-bt";
385 shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
386 };
387};
388
389/* GPS */
390&uart5 {
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_uart5>;
393 status = "okay";
394};
395
396&usbotg {
397 vbus-supply = <&reg_5p0v>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_usbotg>;
400 disable-over-current;
Tim Harvey3deb9892021-03-01 14:33:31 -0800[diff] [blame]401 dr_mode = "host";
Tim Harvey295c8f92021-03-01 14:33:30 -0800[diff] [blame]402 status = "okay";
403};
404
405&usbh1 {
406 status = "okay";
407};
408
409/* Sterling-LWB SDIO WiFi */
410&usdhc2 {
411 pinctrl-names = "default";
412 pinctrl-0 = <&pinctrl_usdhc2>;
413 vmmc-supply = <&reg_wl>;
414 non-removable;
415 bus-width = <4>;
416 status = "okay";
417};
418
419&usdhc3 {
420 pinctrl-names = "default", "state_100mhz", "state_200mhz";
421 pinctrl-0 = <&pinctrl_usdhc3>;
422 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
423 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
424 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
425 vmmc-supply = <&reg_3p3v>;
426 status = "okay";
427};
428
429&wdog1 {
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_wdog>;
432 fsl,ext-reset-output;
433};
434
435&iomuxc {
436 pinctrl_accel: accelmuxgrp {
437 fsl,pins = <
438 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
439 >;
440 };
441
442 pinctrl_bten: btengrp {
443 fsl,pins = <
444 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
445 >;
446 };
447
448 pinctrl_ecspi3: escpi3grp {
449 fsl,pins = <
450 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
451 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
452 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
453 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
454 >;
455 };
456
457 pinctrl_enet: enetgrp {
458 fsl,pins = <
459 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
460 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
461 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
462 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
463 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
464 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
465 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
466 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
467 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
468 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
469 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
470 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
471 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
472 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
473 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
474 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
475 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
476 >;
477 };
478
479 pinctrl_gpio_leds: gpioledsgrp {
480 fsl,pins = <
481 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
482 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
483 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
484 >;
485 };
486
487 pinctrl_gpmi_nand: gpminandgrp {
488 fsl,pins = <
489 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
490 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
491 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
492 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
493 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
494 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
495 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
496 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
497 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
498 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
499 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
500 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
501 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
502 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
503 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
504 >;
505 };
506
507 pinctrl_i2c1: i2c1grp {
508 fsl,pins = <
509 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
510 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
511 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
512 >;
513 };
514
515 pinctrl_i2c2: i2c2grp {
516 fsl,pins = <
517 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
518 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
519 >;
520 };
521
522 pinctrl_i2c3: i2c3grp {
523 fsl,pins = <
524 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
525 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
526 >;
527 };
528
529 pinctrl_pcie: pciegrp {
530 fsl,pins = <
531 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
532 >;
533 };
534
535 pinctrl_pps: ppsgrp {
536 fsl,pins = <
537 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
538 >;
539 };
540
541 pinctrl_pwm2: pwm2grp {
542 fsl,pins = <
543 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
544 >;
545 };
546
547 pinctrl_pwm3: pwm3grp {
548 fsl,pins = <
549 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
550 >;
551 };
552
553 pinctrl_reg_wl: regwlgrp {
554 fsl,pins = <
555 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
556 >;
557 };
558
559 pinctrl_uart1: uart1grp {
560 fsl,pins = <
561 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
562 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
563 >;
564 };
565
566 pinctrl_uart2: uart2grp {
567 fsl,pins = <
568 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
569 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
570 >;
571 };
572
573 pinctrl_uart3: uart3grp {
574 fsl,pins = <
575 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
576 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
577 MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
578 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
579 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
580 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
581 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
582 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
583 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
584 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
585 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
586 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
587 >;
588 };
589
590 pinctrl_uart4: uart4grp {
591 fsl,pins = <
592 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
593 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
594 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
595 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
596 >;
597 };
598
599 pinctrl_uart5: uart5grp {
600 fsl,pins = <
601 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
602 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
603 >;
604 };
605
606 pinctrl_usbotg: usbotggrp {
607 fsl,pins = <
608 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
609 >;
610 };
611
612 pinctrl_usdhc2: usdhc2grp {
613 fsl,pins = <
614 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
615 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
616 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
617 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
618 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
619 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
620 >;
621 };
622
623 pinctrl_usdhc3: usdhc3grp {
624 fsl,pins = <
625 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
626 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
627 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
628 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
629 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
630 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
631 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
632 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
633 >;
634 };
635
636 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
637 fsl,pins = <
638 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
639 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
640 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
641 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
642 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
643 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
644 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
645 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
646 >;
647 };
648
649 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
650 fsl,pins = <
651 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
652 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
653 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
654 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
655 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
656 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
657 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
658 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
659 >;
660 };
661
662 pinctrl_wdog: wdoggrp {
663 fsl,pins = <
664 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
665 >;
666 };
667};