Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 2 | /* |
Wolfgang Denk | f710efd | 2010-07-24 20:22:02 +0200 | [diff] [blame] | 3 | * (C) Copyright 2002-2010 |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __ASM_GBL_DATA_H |
| 8 | #define __ASM_GBL_DATA_H |
Simon Glass | 3ac47d7 | 2012-12-13 20:48:30 +0000 | [diff] [blame] | 9 | |
| 10 | #ifndef __ASSEMBLY__ |
| 11 | |
Tom Rini | 10e6a37 | 2023-12-14 13:16:52 -0500 | [diff] [blame^] | 12 | #include <linux/types.h> |
Simon Glass | 9909bf3 | 2015-08-10 20:44:31 -0600 | [diff] [blame] | 13 | #include <asm/processor.h> |
Simon Glass | c3d0c23 | 2019-12-06 21:42:05 -0700 | [diff] [blame] | 14 | #include <asm/mrccache.h> |
Simon Glass | 9909bf3 | 2015-08-10 20:44:31 -0600 | [diff] [blame] | 15 | |
Simon Glass | 30580fc | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 16 | enum pei_boot_mode_t { |
| 17 | PEI_BOOT_NONE = 0, |
| 18 | PEI_BOOT_SOFT_RESET, |
| 19 | PEI_BOOT_RESUME, |
| 20 | |
| 21 | }; |
| 22 | |
Simon Glass | d21f34e | 2016-03-11 22:07:26 -0700 | [diff] [blame] | 23 | struct dimm_info { |
| 24 | uint32_t dimm_size; |
| 25 | uint16_t ddr_type; |
| 26 | uint16_t ddr_frequency; |
| 27 | uint8_t rank_per_dimm; |
| 28 | uint8_t channel_num; |
| 29 | uint8_t dimm_num; |
| 30 | uint8_t bank_locator; |
| 31 | /* The 5th byte is '\0' for the end of string */ |
| 32 | uint8_t serial[5]; |
| 33 | /* The 19th byte is '\0' for the end of string */ |
| 34 | uint8_t module_part_number[19]; |
| 35 | uint16_t mod_id; |
| 36 | uint8_t mod_type; |
| 37 | uint8_t bus_width; |
| 38 | } __packed; |
| 39 | |
| 40 | struct pei_memory_info { |
| 41 | uint8_t dimm_cnt; |
| 42 | /* Maximum num of dimm is 8 */ |
| 43 | struct dimm_info dimm[8]; |
| 44 | } __packed; |
| 45 | |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 46 | struct memory_area { |
| 47 | uint64_t start; |
| 48 | uint64_t size; |
| 49 | }; |
| 50 | |
| 51 | struct memory_info { |
| 52 | int num_areas; |
| 53 | uint64_t total_memory; |
| 54 | uint64_t total_32bit_memory; |
| 55 | struct memory_area area[CONFIG_NR_DRAM_BANKS]; |
| 56 | }; |
| 57 | |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 58 | #define MAX_MTRR_REQUESTS 8 |
| 59 | |
| 60 | /** |
| 61 | * A request for a memory region to be set up in a particular way. These |
| 62 | * requests are processed before board_init_r() is called. They are generally |
| 63 | * optional and can be ignored with some performance impact. |
| 64 | */ |
| 65 | struct mtrr_request { |
| 66 | int type; /* MTRR_TYPE_... */ |
| 67 | uint64_t start; |
| 68 | uint64_t size; |
| 69 | }; |
| 70 | |
Simon Glass | 91efff5 | 2019-12-06 21:42:07 -0700 | [diff] [blame] | 71 | /** |
| 72 | * struct mrc_output - holds the MRC data |
| 73 | * |
| 74 | * @buf: MRC training data to save for the next boot. This is set to point to |
| 75 | * the raw data after SDRAM init is complete. Then mrccache_setup() |
| 76 | * turns it into a proper cache record with a checksum |
| 77 | * @len: Length of @buf |
| 78 | * @cache: Resulting cache record |
| 79 | */ |
| 80 | struct mrc_output { |
| 81 | char *buf; |
| 82 | uint len; |
| 83 | struct mrc_data_container *cache; |
| 84 | }; |
| 85 | |
Simon Glass | 3ac47d7 | 2012-12-13 20:48:30 +0000 | [diff] [blame] | 86 | /* Architecture-specific global data */ |
| 87 | struct arch_global_data { |
Simon Glass | 9909bf3 | 2015-08-10 20:44:31 -0600 | [diff] [blame] | 88 | u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16); |
Bin Meng | 47eac04 | 2015-01-22 11:29:40 +0800 | [diff] [blame] | 89 | struct global_data *gd_addr; /* Location of Global Data */ |
| 90 | uint8_t x86; /* CPU family */ |
| 91 | uint8_t x86_vendor; /* CPU vendor */ |
| 92 | uint8_t x86_model; |
| 93 | uint8_t x86_mask; |
Bin Meng | 035c1d2 | 2014-11-09 22:18:56 +0800 | [diff] [blame] | 94 | uint32_t x86_device; |
Simon Glass | 6fa6e4a | 2013-02-28 19:26:12 +0000 | [diff] [blame] | 95 | uint64_t tsc_base; /* Initial value returned by rdtsc() */ |
Simon Glass | ed10a4f | 2019-10-20 21:37:47 -0600 | [diff] [blame] | 96 | bool tsc_inited; /* true if tsc is ready for use */ |
Simon Glass | 471919d | 2017-09-05 19:49:46 -0600 | [diff] [blame] | 97 | unsigned long clock_rate; /* Clock rate of timer in Hz */ |
Simon Glass | 347c05b | 2013-02-28 19:26:15 +0000 | [diff] [blame] | 98 | void *new_fdt; /* Relocated FDT */ |
Simon Glass | 1f4476c | 2014-11-06 13:20:10 -0700 | [diff] [blame] | 99 | uint32_t bist; /* Built-in self test value */ |
Simon Glass | 30580fc | 2014-11-12 22:42:23 -0700 | [diff] [blame] | 100 | enum pei_boot_mode_t pei_boot_mode; |
Simon Glass | 60af017 | 2014-11-12 22:42:24 -0700 | [diff] [blame] | 101 | const struct pch_gpio_map *gpio_map; /* board GPIO map */ |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 102 | struct memory_info meminfo; /* Memory information */ |
Simon Glass | d21f34e | 2016-03-11 22:07:26 -0700 | [diff] [blame] | 103 | struct pei_memory_info pei_meminfo; /* PEI memory information */ |
Park, Aiden | 6e3cc36 | 2019-08-03 08:30:12 +0000 | [diff] [blame] | 104 | #ifdef CONFIG_USE_HOB |
Bin Meng | 47eac04 | 2015-01-22 11:29:40 +0800 | [diff] [blame] | 105 | void *hob_list; /* FSP HOB list */ |
Bin Meng | 005f0af | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 106 | #endif |
Simon Glass | 7bf5b9e | 2015-01-01 16:18:07 -0700 | [diff] [blame] | 107 | struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS]; |
| 108 | int mtrr_req_count; |
Bin Meng | 47eac04 | 2015-01-22 11:29:40 +0800 | [diff] [blame] | 109 | int has_mtrr; |
Simon Glass | 91efff5 | 2019-12-06 21:42:07 -0700 | [diff] [blame] | 110 | /* MRC training data */ |
| 111 | struct mrc_output mrc[MRC_TYPE_COUNT]; |
Simon Glass | f95ad8c | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 112 | ulong table; /* Table pointer from previous loader */ |
Simon Glass | 37e706d | 2017-01-16 07:04:17 -0700 | [diff] [blame] | 113 | int turbo_state; /* Current turbo state */ |
Simon Glass | f64d6f7 | 2017-01-16 07:04:16 -0700 | [diff] [blame] | 114 | struct irq_routing_table *pirq_routing_table; |
Simon Glass | f5bdce2 | 2019-12-06 21:41:41 -0700 | [diff] [blame] | 115 | int dw_i2c_num_cards; /* Used by designware i2c driver */ |
Bin Meng | 322ec3e | 2016-05-11 07:44:59 -0700 | [diff] [blame] | 116 | #ifdef CONFIG_SEABIOS |
| 117 | u32 high_table_ptr; |
| 118 | u32 high_table_limit; |
| 119 | #endif |
Bin Meng | 2ee5b85 | 2017-04-21 07:24:33 -0700 | [diff] [blame] | 120 | int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */ |
Bin Meng | 353f5cb | 2017-04-21 07:24:47 -0700 | [diff] [blame] | 121 | ulong backup_mem; /* Backup memory address for S3 */ |
Simon Glass | 26561da | 2019-12-06 21:42:21 -0700 | [diff] [blame] | 122 | #ifdef CONFIG_FSP_VERSION2 |
| 123 | struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */ |
| 124 | #endif |
Simon Glass | d89f193 | 2020-07-16 21:22:30 -0600 | [diff] [blame] | 125 | void *itss_priv; /* Private ITSS data pointer */ |
Simon Glass | fb8736d | 2020-07-16 21:22:34 -0600 | [diff] [blame] | 126 | ulong coreboot_table; /* Address of coreboot table */ |
Simon Glass | 66ca25c | 2023-07-15 21:39:10 -0600 | [diff] [blame] | 127 | ulong table_start; /* Start address of x86 tables */ |
| 128 | ulong table_end; /* End address of x86 tables */ |
| 129 | ulong table_start_high; /* Start address of high x86 tables */ |
| 130 | ulong table_end_high; /* End address of high x86 tables */ |
Simon Glass | 9b38810 | 2023-09-19 21:00:15 -0600 | [diff] [blame] | 131 | ulong smbios_start; /* Start address of SMBIOS table */ |
Simon Glass | 3ac47d7 | 2012-12-13 20:48:30 +0000 | [diff] [blame] | 132 | }; |
| 133 | |
Graeme Russ | 3c28f48 | 2011-09-01 00:48:27 +0000 | [diff] [blame] | 134 | #endif |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 135 | |
Simon Glass | d388763 | 2012-12-13 20:49:27 +0000 | [diff] [blame] | 136 | #include <asm-generic/global_data.h> |
| 137 | |
| 138 | #ifndef __ASSEMBLY__ |
Simon Glass | 590aef7 | 2017-01-16 07:03:59 -0700 | [diff] [blame] | 139 | # if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64) |
Simon Glass | 7f65c09 | 2015-07-31 09:31:35 -0600 | [diff] [blame] | 140 | |
Simon Glass | 590aef7 | 2017-01-16 07:03:59 -0700 | [diff] [blame] | 141 | /* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */ |
Simon Glass | 7f65c09 | 2015-07-31 09:31:35 -0600 | [diff] [blame] | 142 | #define gd global_data_ptr |
| 143 | |
| 144 | #define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr |
| 145 | # else |
Simon Glass | 56da76d | 2022-12-21 16:08:15 -0700 | [diff] [blame] | 146 | static inline notrace gd_t *get_fs_gd_ptr(void) |
Graeme Russ | 3536896 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 147 | { |
| 148 | gd_t *gd_ptr; |
| 149 | |
Simon Glass | 590aef7 | 2017-01-16 07:03:59 -0700 | [diff] [blame] | 150 | #if CONFIG_IS_ENABLED(X86_64) |
| 151 | asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr)); |
| 152 | #else |
Graeme Russ | 3536896 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 153 | asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr)); |
Simon Glass | 590aef7 | 2017-01-16 07:03:59 -0700 | [diff] [blame] | 154 | #endif |
Graeme Russ | 3536896 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 155 | |
| 156 | return gd_ptr; |
| 157 | } |
| 158 | |
| 159 | #define gd get_fs_gd_ptr() |
Graeme Russ | 5fb91cc | 2010-10-07 20:03:29 +1100 | [diff] [blame] | 160 | |
Simon Glass | 5d18dc9 | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 161 | #define DECLARE_GLOBAL_DATA_PTR |
Simon Glass | 7f65c09 | 2015-07-31 09:31:35 -0600 | [diff] [blame] | 162 | # endif |
Simon Glass | 5d18dc9 | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 163 | |
Graeme Russ | 5fb91cc | 2010-10-07 20:03:29 +1100 | [diff] [blame] | 164 | #endif |
| 165 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 166 | #endif /* __ASM_GBL_DATA_H */ |