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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +02002/*
3 * (C) Copyright 2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +02005 */
6
7/*
8 * This file contains the configuration parameters for qemu-mips64 target.
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020014#define CONFIG_QEMU_MIPS
Daniel Schwierzeckac25adf2014-11-15 23:30:01 +010015
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020016#define CONFIG_MISC_INIT_R
17
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020018#define CONFIG_TIMESTAMP /* Print image info with timestamp */
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020019
20#define CONFIG_EXTRA_ENV_SETTINGS \
21 "addmisc=setenv bootargs ${bootargs} " \
22 "console=ttyS0,${baudrate} " \
23 "panic=1\0" \
24 "bootfile=/tftpboot/vmlinux\0" \
25 "load=tftp ffffffff80500000 ${u-boot}\0" \
26 ""
27
28#define CONFIG_BOOTCOMMAND "bootp;bootelf"
29
30/*
31 * BOOTP options
32 */
33#define CONFIG_BOOTP_BOOTFILESIZE
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020034
35/*
36 * Command line configuration.
37 */
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020038
39#define CONFIG_DRIVER_NE2000
40#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
41
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020042#define CONFIG_SYS_NS16550_SERIAL
43#define CONFIG_SYS_NS16550_REG_SIZE 1
44#define CONFIG_SYS_NS16550_CLK 115200
45#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020046
Stanislav Galabov19030fd2016-02-17 15:23:30 +020047#ifdef CONFIG_SYS_BIG_ENDIAN
48#define CONFIG_IDE_SWAP_IO
49#endif
50
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020051#define CONFIG_SYS_IDE_MAXBUS 2
52#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
53#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
54#define CONFIG_SYS_ATA_DATA_OFFSET 0
55#define CONFIG_SYS_ATA_REG_OFFSET 0
56#define CONFIG_SYS_ATA_BASE_ADDR 0xffffffffb4000000
57
58#define CONFIG_SYS_IDE_MAXDEVICE 4
59
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020060/*
61 * Miscellaneous configurable options
62 */
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020063
Kyle Edwards27e5e132017-04-12 22:42:32 -040064#define CONFIG_SYS_MALLOC_LEN (256 << 10)
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020065
66#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
67
68#define CONFIG_SYS_MHZ 132
69
70#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
71
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020072/* Cached addr */
73#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
74
75/* default load address */
76#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
77
78#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
79#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
80
81/*-----------------------------------------------------------------------
82 * FLASH and environment organization
83 */
84/* The following #defines are needed to get flash environment right */
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020085#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020086
87#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
88
89/* We boot from this flash, selected with dip switch */
90#define CONFIG_SYS_FLASH_BASE 0xffffffffbfc00000
91#define CONFIG_SYS_MAX_FLASH_BANKS 1
92#define CONFIG_SYS_MAX_FLASH_SECT 128
93#define CONFIG_SYS_FLASH_CFI
94#define CONFIG_FLASH_CFI_DRIVER
95#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
96
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +020097/* Address and size of Primary Environment Sector */
98#define CONFIG_ENV_SIZE 0x8000
Kyle Edwards07531c12017-04-12 22:42:31 -040099#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE)
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200100
101#define CONFIG_ENV_OVERWRITE 1
102
103#define MEM_SIZE 128
104
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200105#endif /* __CONFIG_H */