Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Bo Shen | 8dd5528 | 2012-05-25 00:59:58 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Header file for AT91/AT32 MULTI LAYER LCD Controller |
| 4 | * |
| 5 | * Data structure and register user interface |
| 6 | * |
| 7 | * Copyright (C) 2012 Atmel Corporation |
Bo Shen | 8dd5528 | 2012-05-25 00:59:58 +0000 | [diff] [blame] | 8 | */ |
| 9 | #ifndef __ATMEL_HLCDC_H__ |
| 10 | #define __ATMEL_HLCDC_H__ |
| 11 | |
| 12 | /* Atmel multi layer lcdc hardware registers */ |
| 13 | struct atmel_hlcd_regs { |
| 14 | u32 lcdc_lcdcfg0; |
| 15 | u32 lcdc_lcdcfg1; |
| 16 | u32 lcdc_lcdcfg2; |
| 17 | u32 lcdc_lcdcfg3; |
| 18 | u32 lcdc_lcdcfg4; |
| 19 | u32 lcdc_lcdcfg5; |
| 20 | u32 lcdc_lcdcfg6; |
| 21 | u32 res1; |
| 22 | u32 lcdc_lcden; |
| 23 | u32 lcdc_lcddis; |
| 24 | u32 lcdc_lcdsr; |
| 25 | u32 res2; |
| 26 | u32 lcdc_lcdidr; |
| 27 | u32 res3[3]; |
| 28 | u32 lcdc_basecher; |
| 29 | u32 res4[3]; |
| 30 | u32 lcdc_baseidr; |
| 31 | u32 res5[3]; |
| 32 | u32 lcdc_baseaddr; |
| 33 | u32 lcdc_basectrl; |
| 34 | u32 lcdc_basenext; |
| 35 | u32 lcdc_basecfg0; |
| 36 | u32 lcdc_basecfg1; |
| 37 | u32 lcdc_basecfg2; |
| 38 | u32 lcdc_basecfg3; |
| 39 | u32 lcdc_basecfg4; |
| 40 | }; |
| 41 | |
| 42 | #define LCDC_LCDCFG0_CLKPOL (0x1 << 0) |
| 43 | #define LCDC_LCDCFG0_CLKSEL (0x1 << 2) |
| 44 | #define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3) |
| 45 | #define LCDC_LCDCFG0_CGDISBASE (0x1 << 8) |
| 46 | #define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9) |
| 47 | #define LCDC_LCDCFG0_CGDISHEO (0x1 << 11) |
| 48 | #define LCDC_LCDCFG0_CGDISHCR (0x1 << 12) |
| 49 | #define LCDC_LCDCFG0_CLKDIV_Pos 16 |
| 50 | #define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos) |
| 51 | #define LCDC_LCDCFG0_CLKDIV(value) \ |
| 52 | ((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos))) |
| 53 | |
| 54 | #define LCDC_LCDCFG1_HSPW_Pos 0 |
| 55 | #define LCDC_LCDCFG1_HSPW_Msk (0x3f << LCDC_LCDCFG1_HSPW_Pos) |
| 56 | #define LCDC_LCDCFG1_HSPW(value) \ |
| 57 | ((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos))) |
| 58 | #define LCDC_LCDCFG1_VSPW_Pos 16 |
| 59 | #define LCDC_LCDCFG1_VSPW_Msk (0x3f << LCDC_LCDCFG1_VSPW_Pos) |
| 60 | #define LCDC_LCDCFG1_VSPW(value) \ |
| 61 | ((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos))) |
| 62 | |
| 63 | #define LCDC_LCDCFG2_VFPW_Pos 0 |
| 64 | #define LCDC_LCDCFG2_VFPW_Msk (0x3f << LCDC_LCDCFG2_VFPW_Pos) |
| 65 | #define LCDC_LCDCFG2_VFPW(value) \ |
| 66 | ((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos))) |
| 67 | #define LCDC_LCDCFG2_VBPW_Pos 16 |
| 68 | #define LCDC_LCDCFG2_VBPW_Msk (0x3f << LCDC_LCDCFG2_VBPW_Pos) |
| 69 | #define LCDC_LCDCFG2_VBPW(value) \ |
| 70 | ((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos))) |
| 71 | |
| 72 | #define LCDC_LCDCFG3_HFPW_Pos 0 |
| 73 | #define LCDC_LCDCFG3_HFPW_Msk (0xff << LCDC_LCDCFG3_HFPW_Pos) |
| 74 | #define LCDC_LCDCFG3_HFPW(value) \ |
| 75 | ((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos))) |
| 76 | #define LCDC_LCDCFG3_HBPW_Pos 16 |
| 77 | #define LCDC_LCDCFG3_HBPW_Msk (0xff << LCDC_LCDCFG3_HBPW_Pos) |
| 78 | #define LCDC_LCDCFG3_HBPW(value) \ |
| 79 | ((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos))) |
| 80 | |
| 81 | #define LCDC_LCDCFG4_PPL_Pos 0 |
| 82 | #define LCDC_LCDCFG4_PPL_Msk (0x7ff << LCDC_LCDCFG4_PPL_Pos) |
| 83 | #define LCDC_LCDCFG4_PPL(value) \ |
| 84 | ((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos))) |
| 85 | #define LCDC_LCDCFG4_RPF_Pos 16 |
| 86 | #define LCDC_LCDCFG4_RPF_Msk (0x7ff << LCDC_LCDCFG4_RPF_Pos) |
| 87 | #define LCDC_LCDCFG4_RPF(value) \ |
| 88 | ((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos))) |
| 89 | |
| 90 | #define LCDC_LCDCFG5_HSPOL (0x1 << 0) |
| 91 | #define LCDC_LCDCFG5_VSPOL (0x1 << 1) |
| 92 | #define LCDC_LCDCFG5_VSPDLYS (0x1 << 2) |
| 93 | #define LCDC_LCDCFG5_VSPDLYE (0x1 << 3) |
| 94 | #define LCDC_LCDCFG5_DISPPOL (0x1 << 4) |
| 95 | #define LCDC_LCDCFG5_SERIAL (0x1 << 5) |
| 96 | #define LCDC_LCDCFG5_DITHER (0x1 << 6) |
| 97 | #define LCDC_LCDCFG5_DISPDLY (0x1 << 7) |
| 98 | #define LCDC_LCDCFG5_MODE_Pos 8 |
| 99 | #define LCDC_LCDCFG5_MODE_Msk (0x3 << LCDC_LCDCFG5_MODE_Pos) |
| 100 | #define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8) |
| 101 | #define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8) |
| 102 | #define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8) |
| 103 | #define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8) |
| 104 | #define LCDC_LCDCFG5_VSPSU (0x1 << 12) |
| 105 | #define LCDC_LCDCFG5_VSPHO (0x1 << 13) |
| 106 | #define LCDC_LCDCFG5_GUARDTIME_Pos 16 |
| 107 | #define LCDC_LCDCFG5_GUARDTIME_Msk (0x1f << LCDC_LCDCFG5_GUARDTIME_Pos) |
| 108 | #define LCDC_LCDCFG5_GUARDTIME(value) \ |
| 109 | ((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos))) |
| 110 | |
| 111 | #define LCDC_LCDCFG6_PWMPS_Pos 0 |
| 112 | #define LCDC_LCDCFG6_PWMPS_Msk (0x7 << LCDC_LCDCFG6_PWMPS_Pos) |
| 113 | #define LCDC_LCDCFG6_PWMPS(value) \ |
| 114 | ((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos))) |
| 115 | #define LCDC_LCDCFG6_PWMPOL (0x1 << 4) |
| 116 | #define LCDC_LCDCFG6_PWMCVAL_Pos 8 |
| 117 | #define LCDC_LCDCFG6_PWMCVAL_Msk (0xff << LCDC_LCDCFG6_PWMCVAL_Pos) |
| 118 | #define LCDC_LCDCFG6_PWMCVAL(value) \ |
| 119 | ((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos))) |
| 120 | |
| 121 | #define LCDC_LCDEN_CLKEN (0x1 << 0) |
| 122 | #define LCDC_LCDEN_SYNCEN (0x1 << 1) |
| 123 | #define LCDC_LCDEN_DISPEN (0x1 << 2) |
| 124 | #define LCDC_LCDEN_PWMEN (0x1 << 3) |
| 125 | |
| 126 | #define LCDC_LCDDIS_CLKDIS (0x1 << 0) |
| 127 | #define LCDC_LCDDIS_SYNCDIS (0x1 << 1) |
| 128 | #define LCDC_LCDDIS_DISPDIS (0x1 << 2) |
| 129 | #define LCDC_LCDDIS_PWMDIS (0x1 << 3) |
| 130 | #define LCDC_LCDDIS_CLKRST (0x1 << 8) |
| 131 | #define LCDC_LCDDIS_SYNCRST (0x1 << 9) |
| 132 | #define LCDC_LCDDIS_DISPRST (0x1 << 10) |
| 133 | #define LCDC_LCDDIS_PWMRST (0x1 << 11) |
| 134 | |
| 135 | #define LCDC_LCDSR_CLKSTS (0x1 << 0) |
| 136 | #define LCDC_LCDSR_LCDSTS (0x1 << 1) |
| 137 | #define LCDC_LCDSR_DISPSTS (0x1 << 2) |
| 138 | #define LCDC_LCDSR_PWMSTS (0x1 << 3) |
| 139 | #define LCDC_LCDSR_SIPSTS (0x1 << 4) |
| 140 | |
| 141 | #define LCDC_LCDIDR_SOFID (0x1 << 0) |
| 142 | #define LCDC_LCDIDR_DISID (0x1 << 1) |
| 143 | #define LCDC_LCDIDR_DISPID (0x1 << 2) |
| 144 | #define LCDC_LCDIDR_FIFOERRID (0x1 << 4) |
| 145 | #define LCDC_LCDIDR_BASEID (0x1 << 8) |
| 146 | #define LCDC_LCDIDR_OVR1ID (0x1 << 9) |
| 147 | #define LCDC_LCDIDR_HEOID (0x1 << 11) |
| 148 | #define LCDC_LCDIDR_HCRID (0x1 << 12) |
| 149 | |
| 150 | #define LCDC_BASECHER_CHEN (0x1 << 0) |
| 151 | #define LCDC_BASECHER_UPDATEEN (0x1 << 1) |
| 152 | #define LCDC_BASECHER_A2QEN (0x1 << 2) |
| 153 | |
| 154 | #define LCDC_BASEIDR_DMA (0x1 << 2) |
| 155 | #define LCDC_BASEIDR_DSCR (0x1 << 3) |
| 156 | #define LCDC_BASEIDR_ADD (0x1 << 4) |
| 157 | #define LCDC_BASEIDR_DONE (0x1 << 5) |
| 158 | #define LCDC_BASEIDR_OVR (0x1 << 6) |
| 159 | |
| 160 | #define LCDC_BASECTRL_DFETCH (0x1 << 0) |
| 161 | #define LCDC_BASECTRL_LFETCH (0x1 << 1) |
| 162 | #define LCDC_BASECTRL_DMAIEN (0x1 << 2) |
| 163 | #define LCDC_BASECTRL_DSCRIEN (0x1 << 3) |
| 164 | #define LCDC_BASECTRL_ADDIEN (0x1 << 4) |
| 165 | #define LCDC_BASECTRL_DONEIEN (0x1 << 5) |
| 166 | |
| 167 | #define LCDC_BASECFG0_BLEN_Pos 4 |
| 168 | #define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4) |
| 169 | #define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4) |
| 170 | #define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4) |
| 171 | #define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4) |
| 172 | #define LCDC_BASECFG0_DLBO (0x1 << 8) |
| 173 | |
| 174 | #define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) |
| 175 | #define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) |
| 176 | #define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) |
| 177 | #define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) |
| 178 | #define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) |
| 179 | #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) |
| 180 | #define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) |
| 181 | #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) |
| 182 | #define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) |
| 183 | #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) |
| 184 | #define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) |
| 185 | #define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) |
| 186 | #define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) |
| 187 | #define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) |
| 188 | |
| 189 | #define LCDC_BASECFG2_XSTRIDE_Pos 0 |
| 190 | #define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos) |
| 191 | #define LCDC_BASECFG2_XSTRIDE(value) \ |
| 192 | ((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos))) |
| 193 | |
| 194 | #define LCDC_BASECFG3_BDEF_Pos 0 |
| 195 | #define LCDC_BASECFG3_BDEF_Msk (0xff << LCDC_BASECFG3_BDEF_Pos) |
| 196 | #define LCDC_BASECFG3_BDEF(value) \ |
| 197 | ((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos))) |
| 198 | #define LCDC_BASECFG3_GDEF_Pos 8 |
| 199 | #define LCDC_BASECFG3_GDEF_Msk (0xff << LCDC_BASECFG3_GDEF_Pos) |
| 200 | #define LCDC_BASECFG3_GDEF(value) \ |
| 201 | ((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos))) |
| 202 | #define LCDC_BASECFG3_RDEF_Pos 16 |
| 203 | #define LCDC_BASECFG3_RDEF_Msk (0xff << LCDC_BASECFG3_RDEF_Pos) |
| 204 | #define LCDC_BASECFG3_RDEF(value) \ |
| 205 | ((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos))) |
| 206 | |
Bo Shen | ad5238f | 2012-11-08 17:49:14 +0000 | [diff] [blame] | 207 | #define LCDC_BASECLUT_BCLUT_Pos 0 |
| 208 | #define LCDC_BASECLUT_BCLUT_Msk (0xff << LCDC_BASECLUT_BCLUT_Pos) |
| 209 | #define LCDC_BASECLUT_GCLUT_Pos 8 |
| 210 | #define LCDC_BASECLUT_GCLUT_Msk (0xff << LCDC_BASECLUT_GCLUT_Pos) |
| 211 | #define LCDC_BASECLUT_RCLUT_Pos 16 |
| 212 | #define LCDC_BASECLUT_RCLUT_Msk (0xff << LCDC_BASECLUT_RCLUT_Pos) |
| 213 | |
Bo Shen | 8dd5528 | 2012-05-25 00:59:58 +0000 | [diff] [blame] | 214 | #define LCDC_BASECFG4_DMA (0x1 << 8) |
| 215 | #define LCDC_BASECFG4_REP (0x1 << 9) |
| 216 | |
| 217 | struct lcd_dma_desc { |
| 218 | u32 address; |
| 219 | u32 control; |
| 220 | u32 next; |
| 221 | }; |
| 222 | |
| 223 | #define ATMEL_LCDC_LUT(n) (0x0400 + ((n)*4)) |
| 224 | |
| 225 | #endif /* __ATMEL_HLCDC_H__ */ |