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git01.mediatek.com / filogic / uboot / 10e4779db8ae6c2784392fa7a1f690645918662d / . / board / terasic / de0-nano-soc / qts / sdram_config.h
blob: 0504dd688f9b9d7422d16f764f06e4905eebfd5c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame^]1/* SPDX-License-Identifier: BSD-3-Clause */
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]2/*
3 * Altera SoCFPGA SDRAM configuration
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]4 */
5#ifndef __SDRAM_CONFIG_H
6#define __SDRAM_CONFIG_H
7
8#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
9#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
10#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
11#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0
12#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0
13#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
14#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
15#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
16#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
17#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7
18#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
19#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
20#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
21#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15
22#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120
23#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
24#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
25#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
26#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
27#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
28#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
29#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
30#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
31#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
32#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
33#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
34#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
35#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
36#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
37#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
38#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
39#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
40#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
41#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
42#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
43#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
Chin Liang Seeff38f262016-09-21 10:26:03 +0800[diff] [blame]44#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
45#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
46#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]47#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
48#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
49#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
50#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
51#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
52#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
53#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
54#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
55#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
56#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
57#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
58#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
59#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
60#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
61
62#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
63#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
64#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
65#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
66#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
67#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
68#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
69#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
70#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
71#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
72#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
73#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
74#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
75#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
76#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
77#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
78#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1
79#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1
80#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3
81#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311
82
83/* Sequencer auto configuration */
84#define RW_MGR_ACTIVATE_0_AND_1 0x0D
85#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
86#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
87#define RW_MGR_ACTIVATE_1 0x0F
88#define RW_MGR_CLEAR_DQS_ENABLE 0x49
89#define RW_MGR_GUARANTEED_READ 0x4C
90#define RW_MGR_GUARANTEED_READ_CONT 0x54
91#define RW_MGR_GUARANTEED_WRITE 0x18
92#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B
93#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F
94#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19
95#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D
96#define RW_MGR_IDLE 0x00
97#define RW_MGR_IDLE_LOOP1 0x7B
98#define RW_MGR_IDLE_LOOP2 0x7A
99#define RW_MGR_INIT_RESET_0_CKE_0 0x6F
100#define RW_MGR_INIT_RESET_1_CKE_0 0x74
101#define RW_MGR_LFSR_WR_RD_BANK_0 0x22
102#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25
103#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24
104#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23
105#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32
106#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21
107#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36
108#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39
109#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38
110#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37
111#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46
112#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35
113#define RW_MGR_MRS0_DLL_RESET 0x02
114#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
115#define RW_MGR_MRS0_USER 0x07
116#define RW_MGR_MRS0_USER_MIRR 0x0C
117#define RW_MGR_MRS1 0x03
118#define RW_MGR_MRS1_MIRR 0x09
119#define RW_MGR_MRS2 0x04
120#define RW_MGR_MRS2_MIRR 0x0A
121#define RW_MGR_MRS3 0x05
122#define RW_MGR_MRS3_MIRR 0x0B
123#define RW_MGR_PRECHARGE_ALL 0x12
124#define RW_MGR_READ_B2B 0x59
125#define RW_MGR_READ_B2B_WAIT1 0x61
126#define RW_MGR_READ_B2B_WAIT2 0x6B
127#define RW_MGR_REFRESH_ALL 0x14
128#define RW_MGR_RETURN 0x01
129#define RW_MGR_SGLE_READ 0x7D
130#define RW_MGR_ZQCL 0x06
131
132/* Sequencer defines configuration */
133#define AFI_RATE_RATIO 1
134#define CALIB_LFIFO_OFFSET 8
135#define CALIB_VFIFO_OFFSET 6
136#define ENABLE_SUPER_QUICK_CALIBRATION 0
137#define IO_DELAY_PER_DCHAIN_TAP 25
138#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
139#define IO_DELAY_PER_OPA_TAP 312
140#define IO_DLL_CHAIN_LENGTH 8
141#define IO_DQDQS_OUT_PHASE_MAX 0
142#define IO_DQS_EN_DELAY_MAX 31
143#define IO_DQS_EN_DELAY_OFFSET 0
144#define IO_DQS_EN_PHASE_MAX 7
145#define IO_DQS_IN_DELAY_MAX 31
146#define IO_DQS_IN_RESERVE 4
147#define IO_DQS_OUT_RESERVE 4
148#define IO_IO_IN_DELAY_MAX 31
149#define IO_IO_OUT1_DELAY_MAX 31
150#define IO_IO_OUT2_DELAY_MAX 0
151#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
152#define MAX_LATENCY_COUNT_WIDTH 5
153#define READ_VALID_FIFO_SIZE 16
154#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
155#define RW_MGR_MEM_ADDRESS_MIRRORING 0
156#define RW_MGR_MEM_DATA_MASK_WIDTH 4
157#define RW_MGR_MEM_DATA_WIDTH 32
158#define RW_MGR_MEM_DQ_PER_READ_DQS 8
159#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
160#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
161#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
162#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
163#define RW_MGR_MEM_NUMBER_OF_RANKS 1
164#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
165#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
166#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
167#define TINIT_CNTR0_VAL 99
168#define TINIT_CNTR1_VAL 32
169#define TINIT_CNTR2_VAL 32
170#define TRESET_CNTR0_VAL 99
171#define TRESET_CNTR1_VAL 99
172#define TRESET_CNTR2_VAL 10
173
174/* Sequencer ac_rom_init configuration */
175const u32 ac_rom_init[] = {
176 0x20700000,
177 0x20780000,
178 0x10080431,
179 0x10080530,
180 0x10090044,
181 0x100a0010,
182 0x100b0000,
183 0x10380400,
184 0x10080449,
185 0x100804c8,
186 0x100a0024,
187 0x10090008,
188 0x100b0000,
189 0x30780000,
190 0x38780000,
191 0x30780000,
192 0x10680000,
193 0x106b0000,
194 0x10280400,
195 0x10480000,
196 0x1c980000,
197 0x1c9b0000,
198 0x1c980008,
199 0x1c9b0008,
200 0x38f80000,
201 0x3cf80000,
202 0x38780000,
203 0x18180000,
204 0x18980000,
205 0x13580000,
206 0x135b0000,
207 0x13580008,
208 0x135b0008,
209 0x33780000,
210 0x10580008,
211 0x10780000
212};
213
214/* Sequencer inst_rom_init configuration */
215const u32 inst_rom_init[] = {
216 0x80000,
217 0x80680,
218 0x8180,
219 0x8200,
220 0x8280,
221 0x8300,
222 0x8380,
223 0x8100,
224 0x8480,
225 0x8500,
226 0x8580,
227 0x8600,
228 0x8400,
229 0x800,
230 0x8680,
231 0x880,
232 0xa680,
233 0x80680,
234 0x900,
235 0x80680,
236 0x980,
237 0xa680,
238 0x8680,
239 0x80680,
240 0xb68,
241 0xcce8,
242 0xae8,
243 0x8ce8,
244 0xb88,
245 0xec88,
246 0xa08,
247 0xac88,
248 0x80680,
249 0xce00,
250 0xcd80,
251 0xe700,
252 0xc00,
253 0x20ce0,
254 0x20ce0,
255 0x20ce0,
256 0x20ce0,
257 0xd00,
258 0x680,
259 0x680,
260 0x680,
261 0x680,
262 0x60e80,
263 0x61080,
264 0x61080,
265 0x61080,
266 0xa680,
267 0x8680,
268 0x80680,
269 0xce00,
270 0xcd80,
271 0xe700,
272 0xc00,
273 0x30ce0,
274 0x30ce0,
275 0x30ce0,
276 0x30ce0,
277 0xd00,
278 0x680,
279 0x680,
280 0x680,
281 0x680,
282 0x70e80,
283 0x71080,
284 0x71080,
285 0x71080,
286 0xa680,
287 0x8680,
288 0x80680,
289 0x1158,
290 0x6d8,
291 0x80680,
292 0x1168,
293 0x7e8,
294 0x7e8,
295 0x87e8,
296 0x40fe8,
297 0x410e8,
298 0x410e8,
299 0x410e8,
300 0x1168,
301 0x7e8,
302 0x7e8,
303 0xa7e8,
304 0x80680,
305 0x40e88,
306 0x41088,
307 0x41088,
308 0x41088,
309 0x40f68,
310 0x410e8,
311 0x410e8,
312 0x410e8,
313 0xa680,
314 0x40fe8,
315 0x410e8,
316 0x410e8,
317 0x410e8,
318 0x41008,
319 0x41088,
320 0x41088,
321 0x41088,
322 0x1100,
323 0xc680,
324 0x8680,
325 0xe680,
326 0x80680,
327 0x0,
328 0x8000,
329 0xa000,
330 0xc000,
331 0x80000,
332 0x80,
333 0x8080,
334 0xa080,
335 0xc080,
336 0x80080,
337 0x9180,
338 0x8680,
339 0xa680,
340 0x80680,
341 0x40f08,
342 0x80680
343};
344#endif /*#ifndef__SDRAM_CONFIG_H */