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git01.mediatek.com / filogic / uboot / 10e4779db8ae6c2784392fa7a1f690645918662d / . / board / mpr2 / lowlevel_init.S
blob: e34a7a9a1759eb67bbd13a3e909fc7b4b1ccbd0d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0+ */
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]2/*
3 * (C) Copyright 2008
4 * Mark Jonas <mark.jonas@de.bosch.com>
5 *
6 * (C) Copyright 2007
7 * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
8 *
9 * board/mpr2/lowlevel_init.S
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]10 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]11#include <asm/macro.h>
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]12
13 .global lowlevel_init
14
15 .text
16 .align 2
17
18lowlevel_init:
19
20/*
21 * Set frequency multipliers and dividers in FRQCR.
22 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]23 write16 WTCSR_A, WTCSR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]24
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]25 write16 WTCNT_A, WTCNT_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]26
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]27 write16 FRQCR_A, FRQCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]28
29/*
30 * Setup CS0 (Flash).
31 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]32 write32 CS0BCR_A, CS0BCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]33
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]34 write32 CS0WCR_A, CS0WCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]35
36/*
37 * Setup CS3 (SDRAM).
38 */
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]39 write32 CS3BCR_A, CS3BCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]40
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]41 write32 CS3WCR_A, CS3WCR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]42
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]43 write32 SDCR_A, SDCR_D1
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]44
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]45 write32 RTCSR_A, RTCSR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]46
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]47 write32 RTCNT_A, RTCNT_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]48
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]49 write32 RTCOR_A, RTCOR_D
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]50
Jean-Christophe PLAGNIOL-VILLARDb9c21722008-12-20 19:29:49 +0100[diff] [blame]51 write32 SDCR_A, SDCR_D2
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]52
53 mov.l SDMR3_A, r1
54 mov.l SDMR3_D, r0
55 add r0, r1
56 mov #0, r0
57 mov.w r0, @r1
58
59 rts
60 nop
61
62 .align 4
63
64/*
65 * Configuration for MPR2 A.3 through A.7
66 */
67
68/*
69 * PLL Settings
70 */
Nobuhiro Iwamatsu471e0ec2010-07-22 16:20:08 +0900[diff] [blame]71FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
72WTCNT_D: .word 0x5A00 /* start counting at zero */
73WTCSR_D: .word 0xA507 /* divide by 4096 */
74.align 2
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]75/*
76 * Spansion S29GL256N11 @ 48 MHz
77 */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]78/* 1 idle cycle inserted, normal space, 16 bit */
79CS0BCR_D: .long 0x12490400
80/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */
81CS0WCR_D: .long 0x00000340
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]82
83/*
84 * Samsung K4S511632B-UL75 @ 48 MHz
85 * Micron MT48LC32M16A2-75 @ 48 MHz
86 */
Jean-Christophe PLAGNIOL-VILLARDbd963702008-12-20 19:29:48 +0100[diff] [blame]87/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
88CS3BCR_D: .long 0x10004400
89/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
90CS3WCR_D: .long 0x00000091
91/* no refresh, 13 rows, 10 cols, NO bank active mode */
92SDCR_D1: .long 0x00000012
93SDCR_D2: .long 0x00000812 /* refresh */
94RTCSR_D: .long 0xA55A0008 /* 1/4, once */
95RTCNT_D: .long 0xA55A005D /* count 93 */
96RTCOR_D: .long 0xa55a005d /* count 93 */
97/* mode register CL2, burst read and SINGLE WRITE */
98SDMR3_D: .long 0x440
Mark Jonas35a398a2008-03-10 11:37:10 +0100[diff] [blame]99
100/*
101 * Registers
102 */
103
104FRQCR_A: .long 0xA415FF80
105WTCNT_A: .long 0xA415FF84
106WTCSR_A: .long 0xA415FF86
107
108#define BSC_BASE 0xA4FD0000
109CS0BCR_A: .long BSC_BASE + 0x04
110CS3BCR_A: .long BSC_BASE + 0x0C
111CS0WCR_A: .long BSC_BASE + 0x24
112CS3WCR_A: .long BSC_BASE + 0x2C
113SDCR_A: .long BSC_BASE + 0x44
114RTCSR_A: .long BSC_BASE + 0x48
115RTCNT_A: .long BSC_BASE + 0x4C
116RTCOR_A: .long BSC_BASE + 0x50
117SDMR3_A: .long BSC_BASE + 0x5000