Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2000-2003 |
| 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 5 | * |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 6 | * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 7 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <config.h> |
| 11 | #include <common.h> |
| 12 | #include <asm/immap.h> |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 13 | #include <asm/io.h> |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 14 | |
| 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| 17 | int checkboard(void) |
| 18 | { |
| 19 | puts("Board: "); |
| 20 | puts("Freescale FireEngine 5373 EVB\n"); |
| 21 | return 0; |
| 22 | }; |
| 23 | |
Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 24 | int dram_init(void) |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 25 | { |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 26 | sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 27 | u32 dramsize, i; |
| 28 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 29 | dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 30 | |
| 31 | for (i = 0x13; i < 0x20; i++) { |
| 32 | if (dramsize == (1 << i)) |
| 33 | break; |
| 34 | } |
| 35 | i--; |
| 36 | |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 37 | out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i); |
| 38 | out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); |
| 39 | out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2); |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 40 | |
| 41 | /* Issue PALL */ |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 42 | out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 43 | |
| 44 | /* Issue LEMR */ |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 45 | out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); |
| 46 | out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000); |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 47 | |
| 48 | udelay(500); |
| 49 | |
| 50 | /* Issue PALL */ |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 51 | out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2); |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 52 | |
| 53 | /* Perform two refresh cycles */ |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 54 | out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); |
| 55 | out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 56 | |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 57 | out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE); |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 58 | |
Alison Wang | 35d23df | 2012-03-26 21:49:05 +0000 | [diff] [blame] | 59 | out_be32(&sdram->ctrl, |
| 60 | (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00); |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 61 | |
| 62 | udelay(100); |
| 63 | |
Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 64 | gd->ram_size = dramsize; |
| 65 | |
| 66 | return 0; |
TsiChungLiew | f7d060c | 2008-01-14 17:19:54 -0600 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | int testdram(void) |
| 70 | { |
| 71 | /* TODO: XXX XXX XXX */ |
| 72 | printf("DRAM test not implemented!\n"); |
| 73 | |
| 74 | return (0); |
| 75 | } |