Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefan Roese | 05d10b5 | 2013-04-17 00:32:43 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Projectiondesign AS |
| 4 | * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg |
| 5 | * |
| 6 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
| 7 | * Jason Liu <r64343@freescale.com> |
| 8 | * |
Jagan Teki | 94de5c1 | 2016-10-08 18:00:14 +0530 | [diff] [blame] | 9 | * Refer doc/README.imximage for more details about how-to configure |
Stefan Roese | 05d10b5 | 2013-04-17 00:32:43 +0000 | [diff] [blame] | 10 | * and create imximage boot image |
| 11 | * |
| 12 | * The syntax is taken as close as possible with the kwbimage |
| 13 | */ |
| 14 | |
| 15 | /* image version */ |
| 16 | |
| 17 | IMAGE_VERSION 2 |
| 18 | |
| 19 | /* |
| 20 | * Boot Device : one of |
| 21 | * sd, nand |
| 22 | */ |
| 23 | BOOT_FROM nand |
| 24 | |
| 25 | /* |
| 26 | * Device Configuration Data (DCD) |
| 27 | * |
| 28 | * Each entry must have the format: |
| 29 | * Addr-type Address Value |
| 30 | * |
| 31 | * where: |
| 32 | * Addr-type register length (1,2 or 4 bytes) |
| 33 | * Address absolute address of the register |
| 34 | * value value to be stored in the register |
| 35 | */ |
| 36 | |
| 37 | #define __ASSEMBLY__ |
| 38 | #include <config.h> |
| 39 | #include "asm/arch/mx6-ddr.h" |
| 40 | #include "asm/arch/iomux.h" |
| 41 | #include "asm/arch/crm_regs.h" |
| 42 | |
| 43 | DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 |
| 44 | DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 |
| 45 | DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 |
| 46 | DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 |
| 47 | DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 |
| 48 | DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 |
| 49 | DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 |
| 50 | DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 |
| 51 | |
| 52 | DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 |
| 53 | DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 |
| 54 | DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 |
| 55 | DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 |
| 56 | DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 |
| 57 | DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 |
| 58 | DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 |
| 59 | DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 |
| 60 | |
| 61 | DATA 4, MX6_IOM_DRAM_CAS, 0x00020030 |
| 62 | DATA 4, MX6_IOM_DRAM_RAS, 0x00020030 |
| 63 | DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 |
| 64 | DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 |
| 65 | |
| 66 | DATA 4, MX6_IOM_DRAM_RESET, 0x00020030 |
| 67 | DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 |
| 68 | DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 |
| 69 | |
| 70 | DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 |
| 71 | |
| 72 | DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 |
| 73 | DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 |
| 74 | |
| 75 | DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 |
| 76 | DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 |
| 77 | DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 |
| 78 | DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 |
| 79 | DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 |
| 80 | DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 |
| 81 | DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 |
| 82 | DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 |
| 83 | DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 |
| 84 | |
| 85 | /* (differential input) */ |
| 86 | DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 |
| 87 | /* disable ddr pullups */ |
| 88 | DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 |
| 89 | /* (differential input) */ |
| 90 | DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 |
| 91 | /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ |
| 92 | DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 |
| 93 | /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ |
| 94 | DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 |
| 95 | |
| 96 | /* Read data DQ Byte0-3 delay */ |
| 97 | DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 |
| 98 | DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 |
| 99 | DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 |
| 100 | DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 |
| 101 | DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 |
| 102 | DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 |
| 103 | DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 |
| 104 | DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 |
| 105 | |
| 106 | /* |
| 107 | * MDMISC mirroring interleaved (row/bank/col) |
| 108 | */ |
| 109 | DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 |
| 110 | |
| 111 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 |
| 112 | DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 |
| 113 | DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 |
| 114 | DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB |
| 115 | DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 |
| 116 | DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 |
| 117 | DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 |
| 118 | DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 |
| 119 | DATA 4, MX6_MMDC_P0_MDASP, 0x00000017 |
| 120 | DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 |
| 121 | DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 |
| 122 | DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A |
| 123 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 |
| 124 | DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B |
| 125 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 |
| 126 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 |
| 127 | DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 |
| 128 | DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 |
| 129 | DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 |
| 130 | DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 |
| 131 | DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 |
| 132 | DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 |
| 133 | DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 |
| 134 | DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 |
| 135 | DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 |
| 136 | DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 |
| 137 | DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 |
| 138 | DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 |
| 139 | DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 |
| 140 | DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B |
| 141 | DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 |
| 142 | DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 |
| 143 | DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 |
| 144 | DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F |
| 145 | DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F |
| 146 | DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 |
| 147 | DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 |
| 148 | DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 |
| 149 | DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 |
| 150 | DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 |
| 151 | DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 |
| 152 | |
| 153 | /* set the default clock gate to save power */ |
| 154 | DATA 4, CCM_CCGR0, 0x00C03F3F |
| 155 | DATA 4, CCM_CCGR1, 0x0030FC03 |
| 156 | DATA 4, CCM_CCGR2, 0x0FFFC000 |
| 157 | DATA 4, CCM_CCGR3, 0x3FF00000 |
| 158 | DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ |
| 159 | DATA 4, CCM_CCGR5, 0x0F0000C3 |
| 160 | DATA 4, CCM_CCGR6, 0x000003FF |
| 161 | |
| 162 | /* enable AXI cache for VDOA/VPU/IPU */ |
| 163 | DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF |
| 164 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
| 165 | DATA 4, MX6_IOMUXC_GPR6, 0x007F007F |
| 166 | DATA 4, MX6_IOMUXC_GPR7, 0x007F007F |