Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Bin Meng | 00ffb4d | 2015-02-02 22:35:23 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
Bin Meng | 00ffb4d | 2015-02-02 22:35:23 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _QUARK_DEVICE_H_ |
| 7 | #define _QUARK_DEVICE_H_ |
| 8 | |
Bin Meng | 5efb415 | 2016-05-25 19:19:09 -0700 | [diff] [blame] | 9 | /* |
| 10 | * Internal PCI device numbers within the SoC. |
| 11 | * |
| 12 | * Note it must start with 0x_ prefix, as the device number macro will be |
| 13 | * included in the ACPI ASL files (see irq_helper.h and irq_route.h). |
| 14 | */ |
Bin Meng | 00ffb4d | 2015-02-02 22:35:23 +0800 | [diff] [blame] | 15 | |
Bin Meng | 5efb415 | 2016-05-25 19:19:09 -0700 | [diff] [blame] | 16 | #define QUARK_HOST_BRIDGE_DEV 0x00 |
Bin Meng | ef9e9f9 | 2015-05-25 22:35:06 +0800 | [diff] [blame] | 17 | #define QUARK_HOST_BRIDGE_FUNC 0 |
| 18 | |
Bin Meng | 5efb415 | 2016-05-25 19:19:09 -0700 | [diff] [blame] | 19 | #define QUARK_DEV_20 0x14 |
Bin Meng | ef9e9f9 | 2015-05-25 22:35:06 +0800 | [diff] [blame] | 20 | #define QUARK_MMC_SDIO_FUNC 0 |
| 21 | #define QUARK_UART0_FUNC 1 |
| 22 | #define QUARK_USB_DEVICE_FUNC 2 |
| 23 | #define QUARK_USB_EHCI_FUNC 3 |
| 24 | #define QUARK_USB_OHCI_FUNC 4 |
| 25 | #define QUARK_UART1_FUNC 5 |
| 26 | #define QUARK_EMAC0_FUNC 6 |
| 27 | #define QUARK_EMAC1_FUNC 7 |
| 28 | |
Bin Meng | 5efb415 | 2016-05-25 19:19:09 -0700 | [diff] [blame] | 29 | #define QUARK_DEV_21 0x15 |
Bin Meng | ef9e9f9 | 2015-05-25 22:35:06 +0800 | [diff] [blame] | 30 | #define QUARK_SPI0_FUNC 0 |
| 31 | #define QUARK_SPI1_FUNC 1 |
| 32 | #define QUARK_I2C_GPIO_FUNC 2 |
| 33 | |
Bin Meng | 5efb415 | 2016-05-25 19:19:09 -0700 | [diff] [blame] | 34 | #define QUARK_DEV_23 0x17 |
Bin Meng | ef9e9f9 | 2015-05-25 22:35:06 +0800 | [diff] [blame] | 35 | #define QUARK_PCIE0_FUNC 0 |
| 36 | #define QUARK_PCIE1_FUNC 1 |
| 37 | |
Bin Meng | 5efb415 | 2016-05-25 19:19:09 -0700 | [diff] [blame] | 38 | #define QUARK_LGC_BRIDGE_DEV 0x1f |
Bin Meng | ef9e9f9 | 2015-05-25 22:35:06 +0800 | [diff] [blame] | 39 | #define QUARK_LGC_BRIDGE_FUNC 0 |
| 40 | |
Bin Meng | 5efb415 | 2016-05-25 19:19:09 -0700 | [diff] [blame] | 41 | #ifndef __ASSEMBLY__ |
| 42 | #include <pci.h> |
| 43 | |
Bin Meng | ef9e9f9 | 2015-05-25 22:35:06 +0800 | [diff] [blame] | 44 | #define QUARK_HOST_BRIDGE \ |
| 45 | PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC) |
| 46 | #define QUARK_MMC_SDIO \ |
| 47 | PCI_BDF(0, QUARK_DEV_20, QUARK_MMC_SDIO_FUNC) |
| 48 | #define QUARK_UART0 \ |
| 49 | PCI_BDF(0, QUARK_DEV_20, QUARK_UART0_FUNC) |
| 50 | #define QUARK_USB_DEVICE \ |
| 51 | PCI_BDF(0, QUARK_DEV_20, QUARK_USB_DEVICE_FUNC) |
| 52 | #define QUARK_USB_EHCI \ |
| 53 | PCI_BDF(0, QUARK_DEV_20, QUARK_USB_EHCI_FUNC) |
| 54 | #define QUARK_USB_OHCI \ |
| 55 | PCI_BDF(0, QUARK_DEV_20, QUARK_USB_OHCI_FUNC) |
| 56 | #define QUARK_UART1 \ |
| 57 | PCI_BDF(0, QUARK_DEV_20, QUARK_UART1_FUNC) |
| 58 | #define QUARK_EMAC0 \ |
| 59 | PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC0_FUNC) |
| 60 | #define QUARK_EMAC1 \ |
| 61 | PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC1_FUNC) |
| 62 | #define QUARK_SPI0 \ |
| 63 | PCI_BDF(0, QUARK_DEV_21, QUARK_SPI0_FUNC) |
| 64 | #define QUARK_SPI1 \ |
| 65 | PCI_BDF(0, QUARK_DEV_21, QUARK_SPI1_FUNC) |
| 66 | #define QUARK_I2C_GPIO \ |
| 67 | PCI_BDF(0, QUARK_DEV_21, QUARK_I2C_GPIO_FUNC) |
| 68 | #define QUARK_PCIE0 \ |
| 69 | PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE0_FUNC) |
| 70 | #define QUARK_PCIE1 \ |
| 71 | PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC) |
| 72 | #define QUARK_LEGACY_BRIDGE \ |
| 73 | PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC) |
Bin Meng | 5efb415 | 2016-05-25 19:19:09 -0700 | [diff] [blame] | 74 | #endif /* __ASSEMBLY__ */ |
Bin Meng | 00ffb4d | 2015-02-02 22:35:23 +0800 | [diff] [blame] | 75 | |
| 76 | #endif /* _QUARK_DEVICE_H_ */ |