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git01.mediatek.com / filogic / uboot / 10e4779db8ae6c2784392fa7a1f690645918662d / . / arch / arm / mach-davinci / include / mach / gpio.h
blob: f1d4d9e9e04fba280f91fa01da5be29ed2b6775f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame^]1/* SPDX-License-Identifier: GPL-2.0+ */
Sandeep Paulraj7f507e82009-09-29 10:02:38 -0400[diff] [blame]2/*
3 * Copyright (C) 2009 Texas Instruments Incorporated
Sandeep Paulraj7f507e82009-09-29 10:02:38 -0400[diff] [blame]4 */
5#ifndef _GPIO_DEFS_H_
6#define _GPIO_DEFS_H_
7
Ajay Kumar Guptabae61dd2009-12-22 10:56:12 +0530[diff] [blame]8#ifndef CONFIG_SOC_DA8XX
Sandeep Paulraj7f507e82009-09-29 10:02:38 -0400[diff] [blame]9#define DAVINCI_GPIO_BINTEN 0x01C67008
10#define DAVINCI_GPIO_BANK01 0x01C67010
11#define DAVINCI_GPIO_BANK23 0x01C67038
12#define DAVINCI_GPIO_BANK45 0x01C67060
13#define DAVINCI_GPIO_BANK67 0x01C67088
14
Ajay Kumar Guptabae61dd2009-12-22 10:56:12 +0530[diff] [blame]15#else /* CONFIG_SOC_DA8XX */
16#define DAVINCI_GPIO_BINTEN 0x01E26008
17#define DAVINCI_GPIO_BANK01 0x01E26010
18#define DAVINCI_GPIO_BANK23 0x01E26038
19#define DAVINCI_GPIO_BANK45 0x01E26060
20#define DAVINCI_GPIO_BANK67 0x01E26088
Heiko Schocher8d510c52011-09-14 19:59:35 +0000[diff] [blame]21#define DAVINCI_GPIO_BANK8 0x01E260B0
Ajay Kumar Guptabae61dd2009-12-22 10:56:12 +0530[diff] [blame]22#endif /* CONFIG_SOC_DA8XX */
23
Sandeep Paulraj7f507e82009-09-29 10:02:38 -0400[diff] [blame]24struct davinci_gpio {
25 unsigned int dir;
26 unsigned int out_data;
27 unsigned int set_data;
28 unsigned int clr_data;
29 unsigned int in_data;
30 unsigned int set_rising;
31 unsigned int clr_rising;
32 unsigned int set_falling;
33 unsigned int clr_falling;
34 unsigned int intstat;
35};
36
37struct davinci_gpio_bank {
38 int num_gpio;
39 unsigned int irq_num;
40 unsigned int irq_mask;
41 unsigned long *in_use;
42 unsigned long base;
43};
44
Ajay Kumar Guptabae61dd2009-12-22 10:56:12 +0530[diff] [blame]45#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
46#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
47#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
48#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
Heiko Schocher8d510c52011-09-14 19:59:35 +0000[diff] [blame]49#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
Ajay Kumar Guptabae61dd2009-12-22 10:56:12 +0530[diff] [blame]50
Laurence Withers3ffd9682011-07-18 09:26:01 -0400[diff] [blame]51#define gpio_status() gpio_info()
52#define GPIO_NAME_SIZE 20
Holger Hans Peter Freyther1356f8e2013-02-07 23:41:01 +0000[diff] [blame]53#if defined(CONFIG_SOC_DM644X)
54/* GPIO0 to GPIO53, omit the V3.3 volts one */
55#define MAX_NUM_GPIOS 70
Tom Rini9dbc8362013-03-11 12:02:40 -0400[diff] [blame]56#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
Tomas Novotny59032872013-02-01 06:46:00 +0000[diff] [blame]57#define MAX_NUM_GPIOS 128
58#else
Laurence Withers3ffd9682011-07-18 09:26:01 -0400[diff] [blame]59#define MAX_NUM_GPIOS 144
Tomas Novotny59032872013-02-01 06:46:00 +0000[diff] [blame]60#endif
Laurence Withers3ffd9682011-07-18 09:26:01 -0400[diff] [blame]61#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
62#define GPIO_BIT(gp) ((gp) & 0x1F)
63
64void gpio_info(void);
65
Sandeep Paulraj7f507e82009-09-29 10:02:38 -0400[diff] [blame]66#endif