| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Yen Lin | 1bf6c77 | 2012-04-02 13:18:49 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2010,2011 |
| 4 | * NVIDIA Corporation <www.nvidia.com> |
| Yen Lin | 1bf6c77 | 2012-04-02 13:18:49 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 7 | #ifndef _TEGRA20_GP_PADCTRL_H_ |
| 8 | #define _TEGRA20_GP_PADCTRL_H_ |
| 9 | |
| 10 | #include <asm/arch-tegra/gp_padctrl.h> |
| Yen Lin | 1bf6c77 | 2012-04-02 13:18:49 +0000 | [diff] [blame] | 11 | |
| 12 | /* APB_MISC_GP and padctrl registers */ |
| 13 | struct apb_misc_gp_ctlr { |
| 14 | u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ |
| 15 | u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ |
| 16 | u32 reserved0[22]; /* 0x08 - 0x5C: */ |
| 17 | u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ |
| 18 | u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ |
| 19 | u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ |
| 20 | u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ |
| 21 | u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ |
| 22 | u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ |
| 23 | u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ |
| 24 | u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ |
| 25 | u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ |
| 26 | u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ |
| 27 | u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ |
| 28 | u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ |
| 29 | u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ |
| 30 | u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ |
| 31 | u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ |
| 32 | u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ |
| 33 | u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ |
| 34 | u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ |
| 35 | u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ |
| 36 | u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ |
| 37 | u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ |
| 38 | u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ |
| 39 | u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ |
| 40 | u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ |
| 41 | u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ |
| 42 | u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ |
| 43 | u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ |
| 44 | u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ |
| 45 | u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ |
| 46 | u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ |
| 47 | }; |
| 48 | |
| Tom Warren | 13ac544 | 2012-12-11 13:34:12 +0000 | [diff] [blame] | 49 | #endif /* _TEGRA20_GP_PADCTRL_H_ */ |