| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Kever Yang | 6f64d00 | 2016-09-01 10:14:20 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016 Rockchip Electronics Co.,Ltd |
| Kever Yang | 6f64d00 | 2016-09-01 10:14:20 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _ASM_ARCH_SYS_PROTO_H |
| 7 | #define _ASM_ARCH_SYS_PROTO_H |
| 8 | |
| Jagan Teki | b0f5295 | 2017-09-27 23:03:11 +0530 | [diff] [blame] | 9 | #ifdef CONFIG_ROCKCHIP_RK3288 |
| 10 | #include <asm/armv7.h> |
| 11 | |
| 12 | static void configure_l2ctlr(void) |
| 13 | { |
| 14 | uint32_t l2ctlr; |
| 15 | |
| 16 | l2ctlr = read_l2ctlr(); |
| 17 | l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ |
| 18 | |
| 19 | /* |
| 20 | * Data RAM write latency: 2 cycles |
| 21 | * Data RAM read latency: 2 cycles |
| 22 | * Data RAM setup latency: 1 cycle |
| 23 | * Tag RAM write latency: 1 cycle |
| 24 | * Tag RAM read latency: 1 cycle |
| 25 | * Tag RAM setup latency: 1 cycle |
| 26 | */ |
| 27 | l2ctlr |= (1 << 3 | 1 << 0); |
| 28 | write_l2ctlr(l2ctlr); |
| 29 | } |
| 30 | #endif /* CONFIG_ROCKCHIP_RK3288 */ |
| 31 | |
| Kever Yang | 6f64d00 | 2016-09-01 10:14:20 +0800 | [diff] [blame] | 32 | #endif /* _ASM_ARCH_SYS_PROTO_H */ |