| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Matt Porter | 57da666 | 2013-03-15 10:07:04 +0000 | [diff] [blame] | 2 | /* |
| 3 | * hardware_am33xx.h |
| 4 | * |
| 5 | * AM33xx hardware specific header |
| 6 | * |
| 7 | * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ |
| Matt Porter | 57da666 | 2013-03-15 10:07:04 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __AM33XX_HARDWARE_AM33XX_H |
| 11 | #define __AM33XX_HARDWARE_AM33XX_H |
| 12 | |
| Matt Porter | 691fbe3 | 2013-03-15 10:07:06 +0000 | [diff] [blame] | 13 | /* Module base addresses */ |
| 14 | |
| 15 | /* UART Base Address */ |
| 16 | #define UART0_BASE 0x44E09000 |
| Landheer-Cieslak, Ronald | 9671986 | 2017-10-25 13:46:53 +0000 | [diff] [blame] | 17 | #define UART1_BASE 0x48022000 |
| 18 | #define UART2_BASE 0x48024000 |
| 19 | #define UART3_BASE 0x481A6000 |
| 20 | #define UART4_BASE 0x481A8000 |
| 21 | #define UART5_BASE 0x481AA000 |
| Matt Porter | 691fbe3 | 2013-03-15 10:07:06 +0000 | [diff] [blame] | 22 | |
| 23 | /* GPIO Base address */ |
| 24 | #define GPIO2_BASE 0x481AC000 |
| 25 | |
| 26 | /* Watchdog Timer */ |
| 27 | #define WDT_BASE 0x44E35000 |
| 28 | |
| 29 | /* Control Module Base Address */ |
| 30 | #define CTRL_BASE 0x44E10000 |
| 31 | #define CTRL_DEVICE_BASE 0x44E10600 |
| 32 | |
| 33 | /* PRCM Base Address */ |
| 34 | #define PRCM_BASE 0x44E00000 |
| Lokesh Vutla | 83269d0 | 2013-07-30 11:36:28 +0530 | [diff] [blame] | 35 | #define CM_PER 0x44E00000 |
| 36 | #define CM_WKUP 0x44E00400 |
| Lokesh Vutla | 1c1a281 | 2013-12-10 15:02:11 +0530 | [diff] [blame] | 37 | #define CM_DPLL 0x44E00500 |
| 38 | #define CM_RTC 0x44E00800 |
| Lokesh Vutla | 83269d0 | 2013-07-30 11:36:28 +0530 | [diff] [blame] | 39 | |
| 40 | #define PRM_RSTCTRL (PRCM_BASE + 0x0F00) |
| 41 | #define PRM_RSTST (PRM_RSTCTRL + 8) |
| Matt Porter | 691fbe3 | 2013-03-15 10:07:06 +0000 | [diff] [blame] | 42 | |
| Matt Porter | 57da666 | 2013-03-15 10:07:04 +0000 | [diff] [blame] | 43 | /* VTP Base address */ |
| 44 | #define VTP0_CTRL_ADDR 0x44E10E0C |
| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 45 | #define VTP1_CTRL_ADDR 0x48140E10 |
| James Doublesin | 53c723b | 2014-12-22 16:26:11 -0600 | [diff] [blame] | 46 | #define PRM_DEVICE_INST 0x44E00F00 |
| Matt Porter | 57da666 | 2013-03-15 10:07:04 +0000 | [diff] [blame] | 47 | |
| 48 | /* DDR Base address */ |
| 49 | #define DDR_PHY_CMD_ADDR 0x44E12000 |
| 50 | #define DDR_PHY_DATA_ADDR 0x44E120C8 |
| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 51 | #define DDR_PHY_CMD_ADDR2 0x47C0C800 |
| 52 | #define DDR_PHY_DATA_ADDR2 0x47C0C8C8 |
| Matt Porter | 57da666 | 2013-03-15 10:07:04 +0000 | [diff] [blame] | 53 | #define DDR_DATA_REGS_NR 2 |
| 54 | |
| TENART Antoine | 35c7e52 | 2013-07-02 12:05:59 +0200 | [diff] [blame] | 55 | #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) |
| 56 | #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE |
| 57 | |
| Matt Porter | 691fbe3 | 2013-03-15 10:07:06 +0000 | [diff] [blame] | 58 | /* CPSW Config space */ |
| 59 | #define CPSW_MDIO_BASE 0x4A101000 |
| 60 | |
| 61 | /* RTC base address */ |
| 62 | #define RTC_BASE 0x44E3E000 |
| 63 | |
| Lokesh Vutla | 83269d0 | 2013-07-30 11:36:28 +0530 | [diff] [blame] | 64 | /* OTG */ |
| 65 | #define USB0_OTG_BASE 0x47401000 |
| 66 | #define USB1_OTG_BASE 0x47401800 |
| 67 | |
| Heiko Schocher | c9a8db8 | 2013-08-19 16:38:57 +0200 | [diff] [blame] | 68 | /* LCD Controller */ |
| 69 | #define LCD_CNTL_BASE 0x4830E000 |
| 70 | |
| 71 | /* PWMSS */ |
| 72 | #define PWMSS0_BASE 0x48300000 |
| 73 | #define AM33XX_ECAP0_BASE 0x48300100 |
| tomas.melin@vaisala.com | cf1fcf4 | 2016-09-16 10:21:39 +0000 | [diff] [blame] | 74 | #define AM33XX_EPWM_BASE 0x48300200 |
| Heiko Schocher | c9a8db8 | 2013-08-19 16:38:57 +0200 | [diff] [blame] | 75 | |
| Matt Porter | 57da666 | 2013-03-15 10:07:04 +0000 | [diff] [blame] | 76 | #endif /* __AM33XX_HARDWARE_AM33XX_H */ |