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git01.mediatek.com / filogic / uboot / 10e4779db8ae6c2784392fa7a1f690645918662d / . / arch / arm / dts / rk3128.dtsi
blob: 5d2499c132449ea13a5522e2b47b476ef3b1b06c [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
Kever Yange43e7392017-11-28 16:04:15 +0800[diff] [blame]2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
Kever Yange43e7392017-11-28 16:04:15 +0800[diff] [blame]4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/pinctrl/rockchip.h>
10#include <dt-bindings/clock/rk3128-cru.h>
11#include "skeleton.dtsi"
12
13/ {
14 compatible = "rockchip,rk3128";
15 rockchip,sram = <&sram>;
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 i2c0 = &i2c0;
26 i2c1 = &i2c1;
27 i2c2 = &i2c2;
28 i2c3 = &i2c3;
29 spi0 = &spi0;
30 serial0 = &uart0;
31 serial1 = &uart1;
32 serial2 = &uart2;
33 mmc0 = &emmc;
34 mmc1 = &sdmmc;
35 };
36
37 memory {
38 device_type = "memory";
39 reg = <0x60000000 0x40000000>;
40 };
41
42 arm-pmu {
43 compatible = "arm,cortex-a7-pmu";
44 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53 enable-method = "rockchip,rk3128-smp";
54
55 cpu0:cpu@0x000 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a7";
58 reg = <0x000>;
59 operating-points = <
60 /* KHz uV */
61 816000 1000000
62 >;
63 #cooling-cells = <2>; /* min followed by max */
64 clock-latency = <40000>;
65 clocks = <&cru ARMCLK>;
66 };
67
68 cpu1:cpu@0x001 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a7";
71 reg = <0x001>;
72 };
73
74 cpu2:cpu@0x002 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a7";
77 reg = <0x002>;
78 };
79
80 cpu3:cpu@0x003 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a7";
83 reg = <0x003>;
84 };
85 };
86
87 cpu_axi_bus: cpu_axi_bus {
88 compatible = "rockchip,cpu_axi_bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92
93 qos {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges;
97
98 crypto {
99 reg = <0x10128080 0x20>;
100 };
101
102 core {
103 reg = <0x1012a000 0x20>;
104 };
105
106 peri {
107 reg = <0x1012c000 0x20>;
108 };
109
110 gpu {
111 reg = <0x1012d000 0x20>;
112 };
113
114 vpu {
115 reg = <0x1012e000 0x20>;
116 };
117
118 rga {
119 reg = <0x1012f000 0x20>;
120 };
121 ebc {
122 reg = <0x1012f080 0x20>;
123 };
124
125 iep {
126 reg = <0x1012f100 0x20>;
127 };
128
129 lcdc {
130 reg = <0x1012f180 0x20>;
131 rockchip,priority = <3 3>;
132 };
133
134 vip {
135 reg = <0x1012f200 0x20>;
136 rockchip,priority = <3 3>;
137 };
138 };
139
140 msch {
141 #address-cells = <1>;
142 #size-cells = <1>;
143 ranges;
144
145 msch@10128000 {
146 reg = <0x10128000 0x20>;
147 rockchip,read-latency = <0x3f>;
148 };
149 };
150 };
151
152 psci {
153 compatible = "arm,psci";
154 method = "smc";
155 cpu_suspend = <0x84000001>;
156 cpu_off = <0x84000002>;
157 cpu_on = <0x84000003>;
158 migrate = <0x84000005>;
159 };
160
161 amba {
162 compatible = "arm,amba-bus";
163 #address-cells = <1>;
164 #size-cells = <1>;
165 interrupt-parent = <&gic>;
166 ranges;
167
168 pdma: pdma@20078000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0x20078000 0x4000>;
171 arm,pl330-broken-no-flushp;//2
172 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
174 #dma-cells = <1>;
175 clocks = <&cru ACLK_DMAC2>;
176 clock-names = "apb_pclk";
177 };
178 };
179
180 xin24m: xin24m {
181 compatible = "fixed-clock";
182 clock-frequency = <24000000>;
183 clock-output-names = "xin24m";
184 #clock-cells = <0>;
185 };
186
187 xin12m: xin12m {
188 compatible = "fixed-clock";
189 clocks = <&xin24m>;
190 clock-frequency = <12000000>;
191 clock-output-names = "xin12m";
192 #clock-cells = <0>;
193 };
194
195 timer {
196 compatible = "arm,armv7-timer";
197 arm,cpu-registers-not-fw-configured;
198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
200 clock-frequency = <24000000>;
201 };
202
203 timer@20044000 {
204 compatible = "arm,armv7-timer";
205 reg = <0x20044000 0xb8>;
206 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
207 rockchip,broadcast = <1>;
208 };
209
210 watchdog: wdt@2004c000 {
211 compatible = "rockchip,watch dog";
212 reg = <0x2004c000 0x100>;
213 clock-names = "pclk_wdt";
214 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
215 rockchip,irq = <1>;
216 rockchip,timeout = <60>;
217 rockchip,atboot = <1>;
218 rockchip,debug = <0>;
219 };
220
221 reset: reset@20000110 {
222 compatible = "rockchip,reset";
223 reg = <0x20000110 0x24>;
224 #reset-cells = <1>;
225 };
226
227 nandc: nandc@10500000 {
228 compatible = "rockchip,rk-nandc";
229 reg = <0x10500000 0x4000>;
230 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
233 nandc_id = <0>;
234 clocks = <&cru SCLK_NANDC>,
235 <&cru HCLK_NANDC>,
236 <&cru SRST_NANDC>;
237 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
238 };
239
240 dmc: dmc@20004000 {
241 u-boot,dm-pre-reloc;
242 compatible = "rockchip,rk3128-dmc", "syscon";
243 reg = <0x0 0x20004000 0x0 0x1000>;
244 };
245
246 cru: clock-controller@20000000 {
247 u-boot,dm-pre-reloc;
248 compatible = "rockchip,rk3128-cru";
249 reg = <0x20000000 0x1000>;
250 rockchip,grf = <&grf>;
251 #clock-cells = <1>;
252 #reset-cells = <1>;
253 assigned-clocks = <&cru PLL_GPLL>;
254 assigned-clock-rates = <594000000>;
255 };
256
257 uart0: serial0@20060000 {
258 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
259 reg = <0x20060000 0x100>;
260 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
261 reg-shift = <2>;
262 reg-io-width = <4>;
263 clock-frequency = <24000000>;
264 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
265 clock-names = "baudclk", "apb_pclk";
266 pinctrl-names = "default";
267 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
268 dmas = <&pdma 2>, <&pdma 3>;
269 #dma-cells = <2>;
270 };
271
272 uart1: serial1@20064000 {
273 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
274 reg = <0x20064000 0x100>;
275 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
276 reg-shift = <2>;
277 reg-io-width = <4>;
278 clock-frequency = <24000000>;
279 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
280 clock-names = "baudclk", "apb_pclk";
281 pinctrl-names = "default";
282 pinctrl-0 = <&uart1_xfer>;
283 dmas = <&pdma 4>, <&pdma 5>;
284 #dma-cells = <2>;
285 };
286
287 uart2: serial2@20068000 {
288 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
289 reg = <0x20068000 0x100>;
290 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
291 reg-shift = <2>;
292 reg-io-width = <4>;
293 clock-frequency = <24000000>;
294 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
295 clock-names = "baudclk", "apb_pclk";
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart2_xfer>;
298 dmas = <&pdma 6>, <&pdma 7>;
299 #dma-cells = <2>;
300 };
301
302 saradc: saradc@2006c000 {
303 compatible = "rockchip,saradc";
304 reg = <0x2006c000 0x100>;
305 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
306 #io-channel-cells = <1>;
307 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
308 clock-names = "saradc", "apb_pclk";
309 resets = <&cru SRST_SARADC>;
310 reset-names = "saradc-apb";
311 status = "disabled";
312 };
313
314 pwm0: pwm0@20050000 {
315 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
316 reg = <0x20050000 0x10>;
Kever Yang32e49002018-01-16 16:08:18 +0800[diff] [blame]317 #pwm-cells = <3>;
Kever Yange43e7392017-11-28 16:04:15 +0800[diff] [blame]318 pinctrl-names = "default";
319 pinctrl-0 = <&pwm0_pin>;
320 clocks = <&cru PCLK_PWM>;
321 clock-names = "pwm";
322 };
323
324 pwm1: pwm1@20050010 {
325 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
326 reg = <0x20050010 0x10>;
Kever Yang32e49002018-01-16 16:08:18 +0800[diff] [blame]327 #pwm-cells = <3>;
Kever Yange43e7392017-11-28 16:04:15 +0800[diff] [blame]328 pinctrl-names = "default";
329 pinctrl-0 = <&pwm1_pin>;
330 clocks = <&cru PCLK_PWM>;
331 clock-names = "pwm";
332 };
333
334 pwm2: pwm2@20050020 {
335 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
336 reg = <0x20050020 0x10>;
Kever Yang32e49002018-01-16 16:08:18 +0800[diff] [blame]337 #pwm-cells = <3>;
Kever Yange43e7392017-11-28 16:04:15 +0800[diff] [blame]338 pinctrl-names = "default";
339 pinctrl-0 = <&pwm2_pin>;
340 clocks = <&cru PCLK_PWM>;
341 clock-names = "pwm";
342 };
343
344 pwm3: pwm3@20050030 {
345 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
346 reg = <0x20050030 0x10>;
Kever Yang32e49002018-01-16 16:08:18 +0800[diff] [blame]347 #pwm-cells = <3>;
Kever Yange43e7392017-11-28 16:04:15 +0800[diff] [blame]348 pinctrl-names = "default";
349 pinctrl-0 = <&pwm3_pin>;
350 clocks = <&cru PCLK_PWM>;
351 clock-names = "pwm";
352 };
353
354 sram: sram@10080400 {
355 compatible = "rockchip,rk3128-smp-sram", "mmio-sram";
356 reg = <0x10080400 0x1C00>;
357 map-exec;
358 map-cacheable;
359 };
360
361 pmu: syscon@100a0000 {
362 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
363 reg = <0x100a0000 0x1000>;
364 #address-cells = <1>;
365 #size-cells = <1>;
366 };
367
368 gic: interrupt-controller@10139000 {
369 compatible = "arm,gic-400";
370 interrupt-controller;
371 #interrupt-cells = <3>;
372 #address-cells = <0>;
373 reg = <0x10139000 0x1000>,
374 <0x1013a000 0x1000>,
375 <0x1013c000 0x2000>,
376 <0x1013e000 0x2000>;
377 interrupts = <GIC_PPI 9 0xf04>;
378 };
379
380 u2phy: usb2-phy {
381 compatible = "rockchip,rk3128-usb2phy";
382 reg = <0x017c 0x0c>;
383 rockchip,grf = <&grf>;
384 clocks = <&cru SCLK_OTGPHY0>;
385 clock-names = "phyclk";
386 #clock-cells = <0>;
387 clock-output-names = "usb480m_phy";
388 #phy-cells = <1>;
389 status = "disabled";
390
391 u2phy_otg: otg-port {
392 #phy-cells = <0>;
393 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-names = "otg-bvalid", "otg-id",
397 "linestate";
398 status = "disabled";
399 };
400
401 u2phy_host: host-port {
402 #phy-cells = <0>;
403 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
404 interrupt-names = "linestate";
405 status = "disabled";
406 };
407 };
408
409 usb_otg: usb@10180000 {
410 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
411 "snps,dwc2";
412 reg = <0x10180000 0x40000>;
413 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
414 dr_mode = "otg";
415 g-use-dma;
416 hnp-srp-disable;
417 phys = <&u2phy 0>;
418 phy-names = "usb";
419 status = "disabled";
420 };
421
422 usb_host_ehci: usb@101c0000 {
423 compatible = "generic-ehci";
424 reg = <0x101c0000 0x20000>;
425 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
426 phys = <&u2phy 1>;
427 phy-names = "usb";
428 status = "disabled";
429 };
430
431 usb_host_ohci: usb@101e0000 {
432 compatible = "generic-ohci";
433 reg = <0x101e0000 0x20000>;
434 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
435 phys = <&u2phy 1>;
436 phy-names = "usb";
437 status = "disabled";
438 };
439
440 sdmmc: dwmmc@10214000 {
441 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
442 reg = <0x10214000 0x4000>;
443 max-frequency = <150000000>;
444 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
446 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
447 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
448 fifo-depth = <0x100>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
451 bus-width = <4>;
452 status = "disabled";
453 };
454
455 emmc: dwmmc@1021c000 {
456 u-boot,dm-pre-reloc;
457 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
458 reg = <0x1021c000 0x4000>;
459 max-frequency = <150000000>;
460 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
462 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
463 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
464 bus-width = <8>;
465 default-sample-phase = <158>;
466 num-slots = <1>;
467 fifo-depth = <0x100>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
470 resets = <&cru SRST_EMMC>;
471 reset-names = "reset";
472 status = "disabled";
473 };
474
475 i2c0: i2c0@20072000 {
476 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
477 reg = <20072000 0x1000>;
478 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 clock-names = "i2c";
482 clocks = <&cru PCLK_I2C0>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&i2c0_xfer>;
485 };
486
487 i2c1: i2c1@20056000 {
488 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
489 reg = <0x20056000 0x1000>;
490 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
492 #size-cells = <0>;
493 clock-names = "i2c";
494 clocks = <&cru PCLK_I2C1>;
495 pinctrl-names = "default";
496 pinctrl-0 = <&i2c1_xfer>;
497 };
498
499 i2c2: i2c2@2005a000 {
500 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
501 reg = <0x2005a000 0x1000>;
502 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 clock-names = "i2c";
506 clocks = <&cru PCLK_I2C2>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c2_xfer>;
509 };
510
511 i2c3: i2c3@2005e000 {
512 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
513 reg = <0x2005e000 0x1000>;
514 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 clock-names = "i2c";
518 clocks = <&cru PCLK_I2C3>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&i2c3_xfer>;
521 };
522
523 spi0: spi@20074000 {
524 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
525 reg = <0x20074000 0x1000>;
526 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
531 rockchip,spi-src-clk = <0>;
532 num-cs = <2>;
533 clocks =<&cru SCLK_SPI>, <&cru PCLK_SPI>;
534 clock-names = "spi","pclk_spi0";
535 dmas = <&pdma 8>, <&pdma 9>;
536 #dma-cells = <2>;
537 dma-names = "tx", "rx";
538 };
539
540 grf: syscon@20008000 {
541 u-boot,dm-pre-reloc;
542 compatible = "rockchip,rk3128-grf", "syscon";
543 reg = <0x20008000 0x1000>;
544 };
545
546 pinctrl: pinctrl@20008000 {
547 compatible = "rockchip,rk3128-pinctrl";
548 reg = <0x20008000 0xA8>,
549 <0x200080A8 0x4C>,
550 <0x20008118 0x20>,
551 <0x20008100 0x04>;
552 reg-names = "base", "mux", "pull", "drv";
553 rockchip,grf = <&grf>;
554 #address-cells = <1>;
555 #size-cells = <1>;
556 ranges;
557
558 gpio0: gpio0@2007c000 {
559 compatible = "rockchip,gpio-bank";
560 reg = <0x2007c000 0x100>;
561 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&cru PCLK_GPIO0>;
563 gpio-controller;
564 #gpio-cells = <2>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
567 };
568
569 gpio1: gpio1@20080000 {
570 compatible = "rockchip,gpio-bank";
571 reg = <0x20080000 0x100>;
572 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&cru PCLK_GPIO1>;
574 gpio-controller;
575 #gpio-cells = <2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
578 };
579
580 gpio2: gpio2@20084000 {
581 compatible = "rockchip,gpio-bank";
582 reg = <0x20084000 0x100>;
583 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&cru PCLK_GPIO2>;
585 gpio-controller;
586 #gpio-cells = <2>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
589 };
590
591 gpio3: gpio2@20088000 {
592 compatible = "rockchip,gpio-bank";
593 reg = <0x20088000 0x100>;
594 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&cru PCLK_GPIO3>;
596 gpio-controller;
597 #gpio-cells = <2>;
598 interrupt-controller;
599 #interrupt-cells = <2>;
600 };
601
602 pcfg_pull_up: pcfg-pull-up {
603 bias-pull-up;
604 };
605
606 pcfg_pull_down: pcfg-pull-down {
607 bias-pull-down;
608 };
609
610 pcfg_pull_none: pcfg-pull-none {
611 bias-disable;
612 };
613
614 emmc {
615 /*
616 * We run eMMC at max speed; bump up drive strength.
617 * We also have external pulls, so disable the internal ones.
618 */
619
620 emmc_clk: emmc-clk {
621 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
622 };
623
624 emmc_cmd: emmc-cmd {
625 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
626 };
627
628 emmc_pwren: emmc-pwren {
629 rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>;
630 };
631
632 emmc_bus8: emmc-bus8 {
633 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
634 <1 25 RK_FUNC_2 &pcfg_pull_none>,
635 <1 26 RK_FUNC_2 &pcfg_pull_none>,
636 <1 27 RK_FUNC_2 &pcfg_pull_none>,
637 <1 28 RK_FUNC_2 &pcfg_pull_none>,
638 <1 29 RK_FUNC_2 &pcfg_pull_none>,
639 <1 30 RK_FUNC_2 &pcfg_pull_none>,
640 <1 31 RK_FUNC_2 &pcfg_pull_none>;
641 };
642 };
643
644 nandc{
645 nandc_ale:nandc-ale {
646 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
647 };
648
649 nandc_cle:nandc-cle {
650 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
651 };
652
653 nandc_wrn:nandc-wrn {
654 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
655 };
656
657 nandc_rdn:nandc-rdn {
658 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
659 };
660
661 nandc_rdy:nandc-rdy {
662 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
663 };
664
665 nandc_cs0:nandc-cs0 {
666 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
667 };
668
669 nandc_data: nandc-data {
670 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
671 };
672 };
673
674 uart0 {
675 uart0_xfer: uart0-xfer {
676 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
677 <0 17 RK_FUNC_1 &pcfg_pull_none>;
678 };
679
680 uart0_cts: uart0-cts {
681 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
682 };
683
684 uart0_rts: uart0-rts {
685 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
686 };
687 };
688
689 uart1 {
690 uart1_xfer: uart1-xfer {
691 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
692 <2 23 RK_FUNC_1 &pcfg_pull_none>;
693 };
694 };
695
696 uart2 {
697 uart2_xfer: uart2-xfer {
698 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
699 <1 19 RK_FUNC_2 &pcfg_pull_none>;
700 };
701 };
702
703 sdmmc {
704 sdmmc_clk: sdmmc-clk {
705 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
706 };
707
708 sdmmc_cmd: sdmmc-cmd {
709 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;
710 };
711
712 sdmmc_wp: sdmmc-wp {
713 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;
714 };
715
716 sdmmc_pwren: sdmmc-pwren {
717 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;
718 };
719
720 sdmmc_bus4: sdmmc-bus4 {
721 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,
722 <1 RK_PC3 1 &pcfg_pull_up>,
723 <1 RK_PC4 1 &pcfg_pull_up>,
724 <1 RK_PC5 1 &pcfg_pull_up>;
725 };
726 };
727
728 pwm0 {
729 pwm0_pin: pwm0-pin {
730 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
731 };
732 };
733
734 pwm1 {
735 pwm1_pin: pwm1-pin {
736 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
737 };
738 };
739
740 pwm2 {
741 pwm2_pin: pwm2-pin {
742 rockchip,pins = <0 1 2 &pcfg_pull_none>;
743 };
744 };
745
746 pwm3 {
747 pwm3_pin: pwm3-pin {
748 rockchip,pins = <0 27 1 &pcfg_pull_none>;
749 };
750 };
751
752 i2c0 {
753 i2c0_xfer: i2c0-xfer {
754 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
755 <0 1 RK_FUNC_1 &pcfg_pull_none>;
756 };
757 };
758
759 i2c1 {
760 i2c1_xfer: i2c1-xfer {
761 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
762 <0 3 RK_FUNC_1 &pcfg_pull_none>;
763 };
764 };
765
766 i2c2 {
767 i2c2_xfer: i2c2-xfer {
768 rockchip,pins = <2 20 3 &pcfg_pull_none>,
769 <2 21 3 &pcfg_pull_none>;
770 };
771 };
772
773 i2c3 {
774 i2c3_xfer: i2c3-xfer {
775 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
776 <0 7 RK_FUNC_1 &pcfg_pull_none>;
777 };
778 };
779
780 spi0 {
781 spi0_txd_mux0:spi0-txd-mux0 {
782 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
783 };
784
785 spi0_rxd_mux0:spi0-rxd-mux0 {
786 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
787 };
788
789 spi0_clk_mux0:spi0-clk-mux0 {
790 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
791 };
792
793 spi0_cs0_mux0:spi0-cs0-mux0 {
794 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
795 };
796
797 spi0_cs1_mux0:spi0-cs1-mux0 {
798 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
799 };
800 };
801
802 };
803};