blob: bde6e477b8b04ac65228d5ef105bf498b1c7391b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Marek Vasut648559c2018-01-07 20:18:28 +01002/*
3 * Device Tree Source for the Alt board
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
Marek Vasut648559c2018-01-07 20:18:28 +01006 */
7
8/dts-v1/;
9#include "r8a7794.dtsi"
10#include <dt-bindings/gpio/gpio.h>
11
12/ {
13 model = "Alt";
14 compatible = "renesas,alt", "renesas,r8a7794";
15
16 aliases {
17 serial0 = &scif2;
18 i2c10 = &gpioi2c4;
19 i2c12 = &i2cexio4;
20 };
21
22 chosen {
23 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
24 stdout-path = "serial0:115200n8";
25 };
26
27 memory@40000000 {
28 device_type = "memory";
29 reg = <0 0x40000000 0 0x40000000>;
30 };
31
32 d3_3v: regulator-d3-3v {
33 compatible = "regulator-fixed";
34 regulator-name = "D3.3V";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 regulator-boot-on;
38 regulator-always-on;
39 };
40
41 vcc_sdhi0: regulator-vcc-sdhi0 {
42 compatible = "regulator-fixed";
43
44 regulator-name = "SDHI0 Vcc";
45 regulator-min-microvolt = <3300000>;
46 regulator-max-microvolt = <3300000>;
47
48 gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
49 enable-active-high;
50 };
51
52 vccq_sdhi0: regulator-vccq-sdhi0 {
53 compatible = "regulator-gpio";
54
55 regulator-name = "SDHI0 VccQ";
56 regulator-min-microvolt = <1800000>;
57 regulator-max-microvolt = <3300000>;
58
59 gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
60 gpios-states = <1>;
61 states = <3300000 1
62 1800000 0>;
63 };
64
65 vcc_sdhi1: regulator-vcc-sdhi1 {
66 compatible = "regulator-fixed";
67
68 regulator-name = "SDHI1 Vcc";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71
72 gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
73 enable-active-high;
74 };
75
76 vccq_sdhi1: regulator-vccq-sdhi1 {
77 compatible = "regulator-gpio";
78
79 regulator-name = "SDHI1 VccQ";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <3300000>;
82
83 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
84 gpios-states = <1>;
85 states = <3300000 1
86 1800000 0>;
87 };
88
89 lbsc {
90 #address-cells = <1>;
91 #size-cells = <1>;
92 };
93
94 vga-encoder {
95 compatible = "adi,adv7123";
96
97 ports {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 port@0 {
102 reg = <0>;
103 adv7123_in: endpoint {
104 remote-endpoint = <&du_out_rgb1>;
105 };
106 };
107 port@1 {
108 reg = <1>;
109 adv7123_out: endpoint {
110 remote-endpoint = <&vga_in>;
111 };
112 };
113 };
114 };
115
116 vga {
117 compatible = "vga-connector";
118
119 port {
120 vga_in: endpoint {
121 remote-endpoint = <&adv7123_out>;
122 };
123 };
124 };
125
126 x2_clk: x2-clock {
127 compatible = "fixed-clock";
128 #clock-cells = <0>;
129 clock-frequency = <74250000>;
130 };
131
132 x13_clk: x13-clock {
133 compatible = "fixed-clock";
134 #clock-cells = <0>;
135 clock-frequency = <148500000>;
136 };
137
138 gpioi2c4: i2c-10 {
139 #address-cells = <1>;
140 #size-cells = <0>;
141 compatible = "i2c-gpio";
142 status = "disabled";
143 gpios = <&gpio4 9 GPIO_ACTIVE_HIGH /* sda */
144 &gpio4 8 GPIO_ACTIVE_HIGH /* scl */
145 >;
146 i2c-gpio,delay-us = <5>;
147 };
148
149 /*
150 * I2C4 is routed to EXIO connector B, pins 73 (SCL) + 74 (SDA).
151 * A fallback to GPIO is provided.
152 */
153 i2cexio4: i2c-14 {
154 compatible = "i2c-demux-pinctrl";
155 i2c-parent = <&i2c4>, <&gpioi2c4>;
156 i2c-bus-name = "i2c-exio4";
157 #address-cells = <1>;
158 #size-cells = <0>;
159 };
160};
161
162&du {
163 pinctrl-0 = <&du_pins>;
164 pinctrl-names = "default";
165 status = "okay";
166
167 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
168 <&x13_clk>, <&x2_clk>;
169 clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
170
171 ports {
172 port@1 {
173 endpoint {
174 remote-endpoint = <&adv7123_in>;
175 };
176 };
177 };
178};
179
180&extal_clk {
181 clock-frequency = <20000000>;
182};
183
184&pfc {
185 pinctrl-0 = <&scif_clk_pins>;
186 pinctrl-names = "default";
187
188 du_pins: du {
189 groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
190 function = "du1";
191 };
192
193 scif2_pins: scif2 {
194 groups = "scif2_data";
195 function = "scif2";
196 };
197
198 scif_clk_pins: scif_clk {
199 groups = "scif_clk";
200 function = "scif_clk";
201 };
202
203 ether_pins: ether {
204 groups = "eth_link", "eth_mdio", "eth_rmii";
205 function = "eth";
206 };
207
208 phy1_pins: phy1 {
209 groups = "intc_irq8";
210 function = "intc";
211 };
212
213 i2c1_pins: i2c1 {
214 groups = "i2c1";
215 function = "i2c1";
216 };
217
218 i2c4_pins: i2c4 {
219 groups = "i2c4";
220 function = "i2c4";
221 };
222
223 vin0_pins: vin0 {
224 groups = "vin0_data8", "vin0_clk";
225 function = "vin0";
226 };
227
228 mmcif0_pins: mmcif0 {
229 groups = "mmc_data8", "mmc_ctrl";
230 function = "mmc";
231 };
232
233 sdhi0_pins: sd0 {
234 groups = "sdhi0_data4", "sdhi0_ctrl";
235 function = "sdhi0";
236 power-source = <3300>;
237 };
238
239 sdhi0_pins_uhs: sd0_uhs {
240 groups = "sdhi0_data4", "sdhi0_ctrl";
241 function = "sdhi0";
242 power-source = <1800>;
243 };
244
245 sdhi1_pins: sd1 {
246 groups = "sdhi1_data4", "sdhi1_ctrl";
247 function = "sdhi1";
248 power-source = <3300>;
249 };
250
251 sdhi1_pins_uhs: sd1_uhs {
252 groups = "sdhi1_data4", "sdhi1_ctrl";
253 function = "sdhi1";
254 power-source = <1800>;
255 };
256};
257
258&cmt0 {
259 status = "okay";
260};
261
262&pfc {
263 qspi_pins: qspi {
264 groups = "qspi_ctrl", "qspi_data4";
265 function = "qspi";
266 };
267};
268
269&ether {
270 pinctrl-0 = <&ether_pins &phy1_pins>;
271 pinctrl-names = "default";
272
273 phy-handle = <&phy1>;
274 renesas,ether-link-active-low;
275 status = "okay";
276
277 phy1: ethernet-phy@1 {
278 reg = <1>;
279 interrupt-parent = <&irqc0>;
280 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
281 micrel,led-mode = <1>;
282 };
283};
284
285&mmcif0 {
286 pinctrl-0 = <&mmcif0_pins>;
287 pinctrl-names = "default";
288
289 vmmc-supply = <&d3_3v>;
290 vqmmc-supply = <&d3_3v>;
291 bus-width = <8>;
292 non-removable;
293 status = "okay";
294};
295
296&sdhi0 {
297 pinctrl-0 = <&sdhi0_pins>;
298 pinctrl-1 = <&sdhi0_pins_uhs>;
299 pinctrl-names = "default", "state_uhs";
300
301 vmmc-supply = <&vcc_sdhi0>;
302 vqmmc-supply = <&vccq_sdhi0>;
303 cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
304 wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
305 sd-uhs-sdr50;
306 sd-uhs-sdr104;
307 status = "okay";
308};
309
310&sdhi1 {
311 pinctrl-0 = <&sdhi1_pins>;
312 pinctrl-1 = <&sdhi1_pins_uhs>;
313 pinctrl-names = "default", "state_uhs";
314
315 vmmc-supply = <&vcc_sdhi1>;
316 vqmmc-supply = <&vccq_sdhi1>;
317 cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
318 wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
319 sd-uhs-sdr50;
320 status = "okay";
321};
322
323&i2c1 {
324 pinctrl-0 = <&i2c1_pins>;
325 pinctrl-names = "default";
326
327 status = "okay";
328 clock-frequency = <400000>;
329
330 composite-in@20 {
331 compatible = "adi,adv7180";
332 reg = <0x20>;
333 remote = <&vin0>;
334
335 port {
336 adv7180: endpoint {
337 bus-width = <8>;
338 remote-endpoint = <&vin0ep>;
339 };
340 };
341 };
342};
343
344&i2c4 {
345 pinctrl-0 = <&i2c4_pins>;
346 pinctrl-names = "i2c-exio4";
347};
348
349&vin0 {
350 status = "okay";
351 pinctrl-0 = <&vin0_pins>;
352 pinctrl-names = "default";
353
354 port {
355 #address-cells = <1>;
356 #size-cells = <0>;
357
358 vin0ep: endpoint {
359 remote-endpoint = <&adv7180>;
360 bus-width = <8>;
361 };
362 };
363};
364
365&scif2 {
366 pinctrl-0 = <&scif2_pins>;
367 pinctrl-names = "default";
368
369 status = "okay";
370};
371
372&scif_clk {
373 clock-frequency = <14745600>;
374};
375
376&qspi {
377 pinctrl-0 = <&qspi_pins>;
378 pinctrl-names = "default";
379
380 status = "okay";
381
382 flash@0 {
383 compatible = "spansion,s25fl512s", "jedec,spi-nor";
384 reg = <0>;
385 spi-max-frequency = <30000000>;
386 spi-tx-bus-width = <4>;
387 spi-rx-bus-width = <4>;
388 spi-cpol;
389 spi-cpha;
390 m25p,fast-read;
391
392 partitions {
393 compatible = "fixed-partitions";
394 #address-cells = <1>;
395 #size-cells = <1>;
396
397 partition@0 {
398 label = "loader";
399 reg = <0x00000000 0x00040000>;
400 read-only;
401 };
402 partition@40000 {
403 label = "system";
404 reg = <0x00040000 0x00040000>;
405 read-only;
406 };
407 partition@80000 {
408 label = "user";
409 reg = <0x00080000 0x03f80000>;
410 };
411 };
412 };
413};