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Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +03001/*
2 * include/configs/silk.h
3 * This file is silk board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#ifndef __SILK_H
12#define __SILK_H
13
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030014#include "rcar-gen2-common.h"
15
Marek Vasut52e0ee32018-04-21 16:19:56 +020016#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
17#define STACK_AREA_SIZE 0x00100000
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030018#define LOW_LEVEL_MERAM_STACK \
19 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
20
21/* MEMORY */
22#define RCAR_GEN2_SDRAM_BASE 0x40000000
23#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
24#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
25
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030026/* FLASH */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030027#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030028
29/* SH Ether */
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030030#define CONFIG_SH_ETHER_USE_PORT 0
31#define CONFIG_SH_ETHER_PHY_ADDR 0x1
32#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
33#define CONFIG_SH_ETHER_CACHE_WRITEBACK
34#define CONFIG_SH_ETHER_CACHE_INVALIDATE
35#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030036#define CONFIG_BITBANGMII
37#define CONFIG_BITBANGMII_MULTI
38
39/* Board Clock */
40#define RMOBILE_XTAL_CLK 20000000u
41#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
Marek Vasut52e0ee32018-04-21 16:19:56 +020042#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030043
Marek Vasut52e0ee32018-04-21 16:19:56 +020044#define CONFIG_SYS_TMU_CLK_DIV 4
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030045
Marek Vasut52e0ee32018-04-21 16:19:56 +020046#define CONFIG_EXTRA_ENV_SETTINGS \
47 "fdt_high=0xffffffff\0" \
48 "initrd_high=0xffffffff\0"
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030049
Marek Vasut52e0ee32018-04-21 16:19:56 +020050/* SPL support */
51#define CONFIG_SPL_TEXT_BASE 0xe6300000
52#define CONFIG_SPL_STACK 0xe6340000
53#define CONFIG_SPL_MAX_SIZE 0x4000
54#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
55#ifdef CONFIG_SPL_BUILD
56#define CONFIG_CONS_SCIF2
57#define CONFIG_SH_SCIF_CLK_FREQ 65000000
58#endif
Vladimir Barinovc8c1a3e2015-01-12 19:17:07 +030059
60#endif /* __SILK_H */