TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 1 | /* |
| 2 | * FlexBus Internal Memory Map |
| 3 | * |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __FLEXBUS_H |
| 11 | #define __FLEXBUS_H |
| 12 | |
| 13 | /********************************************************************* |
| 14 | * FlexBus Chip Selects (FBCS) |
| 15 | *********************************************************************/ |
Jason Jin | 9fc768d | 2012-09-20 14:17:46 +0800 | [diff] [blame] | 16 | #ifdef CONFIG_M5235 |
| 17 | typedef struct fbcs { |
| 18 | u16 csar0; /* Chip-select Address */ |
| 19 | u16 res1; |
| 20 | u32 csmr0; /* Chip-select Mask */ |
| 21 | u16 res2; |
| 22 | u16 cscr0; /* Chip-select Control */ |
| 23 | |
| 24 | u16 csar1; |
| 25 | u16 res3; |
| 26 | u32 csmr1; |
| 27 | u16 res4; |
| 28 | u16 cscr1; |
| 29 | |
| 30 | u16 csar2; |
| 31 | u16 res5; |
| 32 | u32 csmr2; |
| 33 | u16 res6; |
| 34 | u16 cscr2; |
| 35 | |
| 36 | u16 csar3; |
| 37 | u16 res7; |
| 38 | u32 csmr3; |
| 39 | u16 res8; |
| 40 | u16 cscr3; |
| 41 | |
| 42 | u16 csar4; |
| 43 | u16 res9; |
| 44 | u32 csmr4; |
| 45 | u16 res10; |
| 46 | u16 cscr4; |
| 47 | |
| 48 | u16 csar5; |
| 49 | u16 res11; |
| 50 | u32 csmr5; |
| 51 | u16 res12; |
| 52 | u16 cscr5; |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 53 | |
Jason Jin | 9fc768d | 2012-09-20 14:17:46 +0800 | [diff] [blame] | 54 | u16 csar6; |
| 55 | u16 res13; |
| 56 | u32 csmr6; |
| 57 | u16 res14; |
| 58 | u16 cscr6; |
| 59 | |
| 60 | u16 csar7; |
| 61 | u16 res15; |
| 62 | u32 csmr7; |
| 63 | u16 res16; |
| 64 | u16 cscr7; |
| 65 | } fbcs_t; |
| 66 | #else |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 67 | typedef struct fbcs { |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 68 | u32 csar0; /* Chip-select Address */ |
| 69 | u32 csmr0; /* Chip-select Mask */ |
| 70 | u32 cscr0; /* Chip-select Control */ |
| 71 | u32 csar1; |
| 72 | u32 csmr1; |
| 73 | u32 cscr1; |
| 74 | u32 csar2; |
| 75 | u32 csmr2; |
| 76 | u32 cscr2; |
| 77 | u32 csar3; |
| 78 | u32 csmr3; |
| 79 | u32 cscr3; |
| 80 | u32 csar4; |
| 81 | u32 csmr4; |
| 82 | u32 cscr4; |
| 83 | u32 csar5; |
| 84 | u32 csmr5; |
| 85 | u32 cscr5; |
| 86 | u32 csar6; |
| 87 | u32 csmr6; |
| 88 | u32 cscr6; |
| 89 | u32 csar7; |
| 90 | u32 csmr7; |
| 91 | u32 cscr7; |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 92 | } fbcs_t; |
Jason Jin | 9fc768d | 2012-09-20 14:17:46 +0800 | [diff] [blame] | 93 | #endif |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 94 | |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 95 | #define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000) |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 96 | |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 97 | #define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16) |
| 98 | #define FBCS_CSMR_BAM_MASK (0x0000FFFF) |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 99 | #define FBCS_CSMR_BAM_4G (0xFFFF0000) |
| 100 | #define FBCS_CSMR_BAM_2G (0x7FFF0000) |
| 101 | #define FBCS_CSMR_BAM_1G (0x3FFF0000) |
| 102 | #define FBCS_CSMR_BAM_1024M (0x3FFF0000) |
| 103 | #define FBCS_CSMR_BAM_512M (0x1FFF0000) |
| 104 | #define FBCS_CSMR_BAM_256M (0x0FFF0000) |
| 105 | #define FBCS_CSMR_BAM_128M (0x07FF0000) |
| 106 | #define FBCS_CSMR_BAM_64M (0x03FF0000) |
| 107 | #define FBCS_CSMR_BAM_32M (0x01FF0000) |
| 108 | #define FBCS_CSMR_BAM_16M (0x00FF0000) |
| 109 | #define FBCS_CSMR_BAM_8M (0x007F0000) |
| 110 | #define FBCS_CSMR_BAM_4M (0x003F0000) |
| 111 | #define FBCS_CSMR_BAM_2M (0x001F0000) |
| 112 | #define FBCS_CSMR_BAM_1M (0x000F0000) |
| 113 | #define FBCS_CSMR_BAM_1024K (0x000F0000) |
| 114 | #define FBCS_CSMR_BAM_512K (0x00070000) |
| 115 | #define FBCS_CSMR_BAM_256K (0x00030000) |
| 116 | #define FBCS_CSMR_BAM_128K (0x00010000) |
| 117 | #define FBCS_CSMR_BAM_64K (0x00000000) |
| 118 | |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 119 | #ifdef CONFIG_M5249 |
| 120 | #define FBCS_CSMR_WP (0x00000080) |
| 121 | #define FBCS_CSMR_AM (0x00000040) |
| 122 | #define FBCS_CSMR_CI (0x00000020) |
| 123 | #define FBCS_CSMR_SC (0x00000010) |
| 124 | #define FBCS_CSMR_SD (0x00000008) |
| 125 | #define FBCS_CSMR_UC (0x00000004) |
| 126 | #define FBCS_CSMR_UD (0x00000002) |
| 127 | #else |
| 128 | #define FBCS_CSMR_WP (0x00000100) |
| 129 | #endif |
| 130 | #define FBCS_CSMR_V (0x00000001) /* Valid bit */ |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 131 | |
Jason Jin | 9fc768d | 2012-09-20 14:17:46 +0800 | [diff] [blame] | 132 | #ifdef CONFIG_M5235 |
| 133 | #define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14) |
| 134 | #define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10) |
| 135 | #define FBCS_CSCR_AA_ON (1 << 8) |
| 136 | #define FBCS_CSCR_AA_OFF (0 << 8) |
| 137 | #define FBCS_CSCR_PS_32 (0 << 6) |
| 138 | #define FBCS_CSCR_PS_16 (2 << 6) |
| 139 | #define FBCS_CSCR_PS_8 (1 << 6) |
| 140 | #define FBCS_CSCR_BEM_ON (1 << 5) |
| 141 | #define FBCS_CSCR_BEM_OFF (0 << 5) |
| 142 | #define FBCS_CSCR_BSTR_ON (1 << 4) |
| 143 | #define FBCS_CSCR_BSTR_OFF (0 << 4) |
| 144 | #define FBCS_CSCR_BSTW_ON (1 << 3) |
| 145 | #define FBCS_CSCR_BSTW_OFF (0 << 3) |
| 146 | #define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0) |
| 147 | #else |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 148 | #define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26) |
| 149 | #define FBCS_CSCR_SWS_MASK (0x03FFFFFF) |
| 150 | #define FBCS_CSCR_SWSEN (0x00800000) |
| 151 | #define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20) |
| 152 | #define FBCS_CSCR_ASET_MASK (0xFFCFFFFF) |
| 153 | #define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18) |
| 154 | #define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF) |
| 155 | #define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16) |
| 156 | #define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF) |
| 157 | #define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10) |
| 158 | #define FBCS_CSCR_WS_MASK (0xFFFF03FF) |
| 159 | #define FBCS_CSCR_SBM (0x00000200) |
| 160 | #define FBCS_CSCR_AA (0x00000100) |
| 161 | #define FBCS_CSCR_PS(x) (((x) & 0x03) << 6) |
| 162 | #define FBCS_CSCR_PS_MASK (0xFFFFFF3F) |
| 163 | #define FBCS_CSCR_BEM (0x00000020) |
| 164 | #define FBCS_CSCR_BSTR (0x00000010) |
| 165 | #define FBCS_CSCR_BSTW (0x00000008) |
| 166 | |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 167 | #define FBCS_CSCR_PS_16 (0x00000080) |
TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 168 | #define FBCS_CSCR_PS_8 (0x00000040) |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 169 | #define FBCS_CSCR_PS_32 (0x00000000) |
Jason Jin | 9fc768d | 2012-09-20 14:17:46 +0800 | [diff] [blame] | 170 | #endif |
TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 171 | |
| 172 | #endif /* __FLEXBUS_H */ |