Blame - arch/blackfin/include/asm/mach-bf533/BF531_def.h - filogic/uboot

Mike Frysinger

66c4cf4

2008-02-04 19:26:55 -0500

[diff] [blame]

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/* DO NOT EDIT THIS FILE

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* Automatically generated by generate-def-headers.xsl

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* DO NOT EDIT THIS FILE

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*/

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#ifndef __BFIN_DEF_ADSP_BF531_proc__

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#define __BFIN_DEF_ADSP_BF531_proc__

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#include "../mach-common/ADSP-EDN-core_def.h"

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Mike Frysinger

e6ca6fb

2010-07-26 01:06:37 -0400

[diff] [blame]

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#define MDMAFLX0_DMACNFG_D 0xFFC00E08

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#define MDMAFLX0_XCOUNT_D 0xFFC00E10

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#define MDMAFLX0_XMODIFY_D 0xFFC00E14

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#define MDMAFLX0_YCOUNT_D 0xFFC00E18

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#define MDMAFLX0_YMODIFY_D 0xFFC00E1C

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#define MDMAFLX0_IRQSTAT_D 0xFFC00E28

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#define MDMAFLX0_PMAP_D 0xFFC00E2C

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#define MDMAFLX0_CURXCOUNT_D 0xFFC00E30

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#define MDMAFLX0_CURYCOUNT_D 0xFFC00E38

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#define MDMAFLX0_DMACNFG_S 0xFFC00E48

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#define MDMAFLX0_XCOUNT_S 0xFFC00E50

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#define MDMAFLX0_XMODIFY_S 0xFFC00E54

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#define MDMAFLX0_YCOUNT_S 0xFFC00E58

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#define MDMAFLX0_YMODIFY_S 0xFFC00E5C

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#define MDMAFLX0_IRQSTAT_S 0xFFC00E68

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#define MDMAFLX0_PMAP_S 0xFFC00E6C

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#define MDMAFLX0_CURXCOUNT_S 0xFFC00E70

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#define MDMAFLX0_CURYCOUNT_S 0xFFC00E78

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#define MDMAFLX1_DMACNFG_D 0xFFC00E88

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#define MDMAFLX1_XCOUNT_D 0xFFC00E90

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#define MDMAFLX1_XMODIFY_D 0xFFC00E94

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#define MDMAFLX1_YCOUNT_D 0xFFC00E98

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#define MDMAFLX1_YMODIFY_D 0xFFC00E9C

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#define MDMAFLX1_IRQSTAT_D 0xFFC00EA8

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#define MDMAFLX1_PMAP_D 0xFFC00EAC

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#define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0

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#define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8

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#define MDMAFLX1_DMACNFG_S 0xFFC00EC8

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#define MDMAFLX1_XCOUNT_S 0xFFC00ED0

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#define MDMAFLX1_XMODIFY_S 0xFFC00ED4

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#define MDMAFLX1_YCOUNT_S 0xFFC00ED8

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#define MDMAFLX1_YMODIFY_S 0xFFC00EDC

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#define MDMAFLX1_IRQSTAT_S 0xFFC00EE8

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#define MDMAFLX1_PMAP_S 0xFFC00EEC

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#define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0

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#define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8

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#define DMAFLX0_DMACNFG 0xFFC00C08

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#define DMAFLX0_XCOUNT 0xFFC00C10

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#define DMAFLX0_XMODIFY 0xFFC00C14

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#define DMAFLX0_YCOUNT 0xFFC00C18

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#define DMAFLX0_YMODIFY 0xFFC00C1C

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#define DMAFLX0_IRQSTAT 0xFFC00C28

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#define DMAFLX0_PMAP 0xFFC00C2C

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#define DMAFLX0_CURXCOUNT 0xFFC00C30

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#define DMAFLX0_CURYCOUNT 0xFFC00C38

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#define DMAFLX1_DMACNFG 0xFFC00C48

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#define DMAFLX1_XCOUNT 0xFFC00C50

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#define DMAFLX1_XMODIFY 0xFFC00C54

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#define DMAFLX1_YCOUNT 0xFFC00C58

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#define DMAFLX1_YMODIFY 0xFFC00C5C

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#define DMAFLX1_IRQSTAT 0xFFC00C68

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#define DMAFLX1_PMAP 0xFFC00C6C

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#define DMAFLX1_CURXCOUNT 0xFFC00C70

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#define DMAFLX1_CURYCOUNT 0xFFC00C78

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#define DMAFLX2_DMACNFG 0xFFC00C88

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#define DMAFLX2_XCOUNT 0xFFC00C90

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#define DMAFLX2_XMODIFY 0xFFC00C94

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#define DMAFLX2_YCOUNT 0xFFC00C98

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#define DMAFLX2_YMODIFY 0xFFC00C9C

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#define DMAFLX2_IRQSTAT 0xFFC00CA8

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#define DMAFLX2_PMAP 0xFFC00CAC

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#define DMAFLX2_CURXCOUNT 0xFFC00CB0

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#define DMAFLX2_CURYCOUNT 0xFFC00CB8

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#define DMAFLX3_DMACNFG 0xFFC00CC8

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#define DMAFLX3_XCOUNT 0xFFC00CD0

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#define DMAFLX3_XMODIFY 0xFFC00CD4

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#define DMAFLX3_YCOUNT 0xFFC00CD8

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#define DMAFLX3_YMODIFY 0xFFC00CDC

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#define DMAFLX3_IRQSTAT 0xFFC00CE8

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#define DMAFLX3_PMAP 0xFFC00CEC

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#define DMAFLX3_CURXCOUNT 0xFFC00CF0

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#define DMAFLX3_CURYCOUNT 0xFFC00CF8

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#define DMAFLX4_DMACNFG 0xFFC00D08

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#define DMAFLX4_XCOUNT 0xFFC00D10

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#define DMAFLX4_XMODIFY 0xFFC00D14

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#define DMAFLX4_YCOUNT 0xFFC00D18

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#define DMAFLX4_YMODIFY 0xFFC00D1C

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#define DMAFLX4_IRQSTAT 0xFFC00D28

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#define DMAFLX4_PMAP 0xFFC00D2C

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#define DMAFLX4_CURXCOUNT 0xFFC00D30

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#define DMAFLX4_CURYCOUNT 0xFFC00D38

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#define DMAFLX5_DMACNFG 0xFFC00D48

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#define DMAFLX5_XCOUNT 0xFFC00D50

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#define DMAFLX5_XMODIFY 0xFFC00D54

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#define DMAFLX5_YCOUNT 0xFFC00D58

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#define DMAFLX5_YMODIFY 0xFFC00D5C

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#define DMAFLX5_IRQSTAT 0xFFC00D68

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#define DMAFLX5_PMAP 0xFFC00D6C

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#define DMAFLX5_CURXCOUNT 0xFFC00D70

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#define DMAFLX5_CURYCOUNT 0xFFC00D78

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#define DMAFLX6_DMACNFG 0xFFC00D88

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#define DMAFLX6_XCOUNT 0xFFC00D90

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#define DMAFLX6_XMODIFY 0xFFC00D94

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#define DMAFLX6_YCOUNT 0xFFC00D98

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#define DMAFLX6_YMODIFY 0xFFC00D9C

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#define DMAFLX6_IRQSTAT 0xFFC00DA8

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#define DMAFLX6_PMAP 0xFFC00DAC

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#define DMAFLX6_CURXCOUNT 0xFFC00DB0

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#define DMAFLX6_CURYCOUNT 0xFFC00DB8

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#define DMAFLX7_DMACNFG 0xFFC00DC8

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#define DMAFLX7_XCOUNT 0xFFC00DD0

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#define DMAFLX7_XMODIFY 0xFFC00DD4

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#define DMAFLX7_YCOUNT 0xFFC00DD8

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#define DMAFLX7_YMODIFY 0xFFC00DDC

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#define DMAFLX7_IRQSTAT 0xFFC00DE8

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#define DMAFLX7_PMAP 0xFFC00DEC

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#define DMAFLX7_CURXCOUNT 0xFFC00DF0

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#define DMAFLX7_CURYCOUNT 0xFFC00DF8

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#define TIMER0_CONFIG 0xFFC00600

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#define TIMER0_COUNTER 0xFFC00604

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#define TIMER0_PERIOD 0xFFC00608

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#define TIMER0_WIDTH 0xFFC0060C

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#define TIMER1_CONFIG 0xFFC00610

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#define TIMER1_COUNTER 0xFFC00614

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#define TIMER1_PERIOD 0xFFC00618

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#define TIMER1_WIDTH 0xFFC0061C

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#define TIMER2_CONFIG 0xFFC00620

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#define TIMER2_COUNTER 0xFFC00624

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#define TIMER2_PERIOD 0xFFC00628

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#define TIMER2_WIDTH 0xFFC0062C

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#define TIMER_ENABLE 0xFFC00640

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#define TIMER_DISABLE 0xFFC00644

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#define TIMER_STATUS 0xFFC00648

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#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */

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#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */

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#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */

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#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */

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#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */

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#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */

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#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */

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#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */

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#define UART_THR 0xFFC00400 /* Transmit Holding */

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#define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */

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#define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */

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#define UART_IER 0xFFC00404

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#define UART_IIR 0xFFC00408

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#define UART_LCR 0xFFC0040C

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#define UART_MCR 0xFFC00410

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#define UART_LSR 0xFFC00414

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#define UART_SCR 0xFFC0041C

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#define UART_RBR 0xFFC00400 /* Receive Buffer */

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#define UART_GCTL 0xFFC00424

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#define SPT0_TX_CONFIG0 0xFFC00800

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#define SPT0_TX_CONFIG1 0xFFC00804

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#define SPT0_RX_CONFIG0 0xFFC00820

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#define SPT0_RX_CONFIG1 0xFFC00824

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#define SPT0_TX 0xFFC00810

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#define SPT0_RX 0xFFC00818

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#define SPT0_TSCLKDIV 0xFFC00808

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#define SPT0_RSCLKDIV 0xFFC00828

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#define SPT0_TFSDIV 0xFFC0080C

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#define SPT0_RFSDIV 0xFFC0082C

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#define SPT0_STAT 0xFFC00830

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#define SPT0_MTCS0 0xFFC00840

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#define SPT0_MTCS1 0xFFC00844

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#define SPT0_MTCS2 0xFFC00848

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#define SPT0_MTCS3 0xFFC0084C

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#define SPT0_MRCS0 0xFFC00850

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#define SPT0_MRCS1 0xFFC00854

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#define SPT0_MRCS2 0xFFC00858

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#define SPT0_MRCS3 0xFFC0085C

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#define SPT0_MCMC1 0xFFC00838

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#define SPT0_MCMC2 0xFFC0083C

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#define SPT0_CHNL 0xFFC00834

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#define SPT1_TX_CONFIG0 0xFFC00900

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#define SPT1_TX_CONFIG1 0xFFC00904

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#define SPT1_RX_CONFIG0 0xFFC00920

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#define SPT1_RX_CONFIG1 0xFFC00924

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#define SPT1_TX 0xFFC00910

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#define SPT1_RX 0xFFC00918

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#define SPT1_TSCLKDIV 0xFFC00908

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#define SPT1_RSCLKDIV 0xFFC00928

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#define SPT1_TFSDIV 0xFFC0090C

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#define SPT1_RFSDIV 0xFFC0092C

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#define SPT1_STAT 0xFFC00930

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#define SPT1_MTCS0 0xFFC00940

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#define SPT1_MTCS1 0xFFC00944

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#define SPT1_MTCS2 0xFFC00948

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#define SPT1_MTCS3 0xFFC0094C

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#define SPT1_MRCS0 0xFFC00950

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#define SPT1_MRCS1 0xFFC00954

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#define SPT1_MRCS2 0xFFC00958

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#define SPT1_MRCS3 0xFFC0095C

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#define SPT1_MCMC1 0xFFC00938

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#define SPT1_MCMC2 0xFFC0093C

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#define SPT1_CHNL 0xFFC00934

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#define PPI_CONTROL 0xFFC01000

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#define PPI_STATUS 0xFFC01004

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#define PPI_DELAY 0xFFC0100C

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#define PPI_COUNT 0xFFC01008

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#define PPI_FRAME 0xFFC01010

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#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */

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#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */

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#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */

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#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */

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#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */

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#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */

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#define SYSCR 0xFFC00104 /* System Configuration register */

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#define CHIPID 0xFFC00014

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#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */

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#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */

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#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */

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#define RTC_STAT 0xFFC00300

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#define RTC_ICTL 0xFFC00304

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#define RTC_ISTAT 0xFFC00308

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#define RTC_SWCNT 0xFFC0030C

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#define RTC_ALARM 0xFFC00310

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#define RTC_PREN 0xFFC00314

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#define SPI_CTL 0xFFC00500

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#define SPI_FLG 0xFFC00504

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#define SPI_STAT 0xFFC00508

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#define SPI_TDBR 0xFFC0050C

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#define SPI_RDBR 0xFFC00510

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#define SPI_BAUD 0xFFC00514

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#define SPI_SHADOW 0xFFC00518

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#define FIO_FLAG_D 0xFFC00700

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#define FIO_FLAG_C 0xFFC00704

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#define FIO_FLAG_S 0xFFC00708

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#define FIO_FLAG_T 0xFFC0070C

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#define FIO_MASKA_D 0xFFC00710

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#define FIO_MASKA_C 0xFFC00714

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#define FIO_MASKA_S 0xFFC00718

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#define FIO_MASKA_T 0xFFC0071C

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#define FIO_MASKB_D 0xFFC00720

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#define FIO_MASKB_C 0xFFC00724

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#define FIO_MASKB_S 0xFFC00728

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#define FIO_MASKB_T 0xFFC0072C

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#define FIO_DIR 0xFFC00730

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#define FIO_POLAR 0xFFC00734

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#define FIO_EDGE 0xFFC00738

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#define FIO_BOTH 0xFFC0073C

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#define FIO_INEN 0xFFC00740

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#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */

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#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */

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#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */

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#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */

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#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */

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#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */

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#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */

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#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */

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#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */

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#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */

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#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */

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#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */

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#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */

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#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */

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#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */

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#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */

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#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */

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#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */

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#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */

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#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */

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#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */

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#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */

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#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */

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#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */

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#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */

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#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */

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#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */

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#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */

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#define DMA0_NEXT_DESC_PTR 0xFFC00C00

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#define DMA0_START_ADDR 0xFFC00C04

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#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */

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#define DMA0_X_COUNT 0xFFC00C10

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#define DMA0_X_MODIFY 0xFFC00C14

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#define DMA0_Y_COUNT 0xFFC00C18

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#define DMA0_Y_MODIFY 0xFFC00C1C

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#define DMA0_CURR_DESC_PTR 0xFFC00C20

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#define DMA0_CURR_ADDR 0xFFC00C24

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#define DMA0_IRQ_STATUS 0xFFC00C28

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#define DMA0_PERIPHERAL_MAP 0xFFC00C2C

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#define DMA0_CURR_X_COUNT 0xFFC00C30

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#define DMA0_CURR_Y_COUNT 0xFFC00C38

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#define DMA1_NEXT_DESC_PTR 0xFFC00C40

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#define DMA1_START_ADDR 0xFFC00C44

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#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */

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#define DMA1_X_COUNT 0xFFC00C50

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#define DMA1_X_MODIFY 0xFFC00C54

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#define DMA1_Y_COUNT 0xFFC00C58

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#define DMA1_Y_MODIFY 0xFFC00C5C

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#define DMA1_CURR_DESC_PTR 0xFFC00C60

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#define DMA1_CURR_ADDR 0xFFC00C64

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#define DMA1_IRQ_STATUS 0xFFC00C68

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#define DMA1_PERIPHERAL_MAP 0xFFC00C6C

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#define DMA1_CURR_X_COUNT 0xFFC00C70

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#define DMA1_CURR_Y_COUNT 0xFFC00C78

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#define DMA2_NEXT_DESC_PTR 0xFFC00C80

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#define DMA2_START_ADDR 0xFFC00C84

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#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */

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#define DMA2_X_COUNT 0xFFC00C90

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#define DMA2_X_MODIFY 0xFFC00C94

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#define DMA2_Y_COUNT 0xFFC00C98

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#define DMA2_Y_MODIFY 0xFFC00C9C

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#define DMA2_CURR_DESC_PTR 0xFFC00CA0

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#define DMA2_CURR_ADDR 0xFFC00CA4

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#define DMA2_IRQ_STATUS 0xFFC00CA8

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#define DMA2_PERIPHERAL_MAP 0xFFC00CAC

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#define DMA2_CURR_X_COUNT 0xFFC00CB0

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#define DMA2_CURR_Y_COUNT 0xFFC00CB8

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#define DMA3_NEXT_DESC_PTR 0xFFC00CC0

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#define DMA3_START_ADDR 0xFFC00CC4

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#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */

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#define DMA3_X_COUNT 0xFFC00CD0

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#define DMA3_X_MODIFY 0xFFC00CD4

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#define DMA3_Y_COUNT 0xFFC00CD8

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#define DMA3_Y_MODIFY 0xFFC00CDC

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#define DMA3_CURR_DESC_PTR 0xFFC00CE0

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#define DMA3_CURR_ADDR 0xFFC00CE4

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#define DMA3_IRQ_STATUS 0xFFC00CE8

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#define DMA3_PERIPHERAL_MAP 0xFFC00CEC

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#define DMA3_CURR_X_COUNT 0xFFC00CF0

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#define DMA3_CURR_Y_COUNT 0xFFC00CF8

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#define DMA4_NEXT_DESC_PTR 0xFFC00D00

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#define DMA4_START_ADDR 0xFFC00D04

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#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */

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#define DMA4_X_COUNT 0xFFC00D10

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#define DMA4_X_MODIFY 0xFFC00D14

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#define DMA4_Y_COUNT 0xFFC00D18

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#define DMA4_Y_MODIFY 0xFFC00D1C

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#define DMA4_CURR_DESC_PTR 0xFFC00D20

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#define DMA4_CURR_ADDR 0xFFC00D24

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#define DMA4_IRQ_STATUS 0xFFC00D28

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#define DMA4_PERIPHERAL_MAP 0xFFC00D2C

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#define DMA4_CURR_X_COUNT 0xFFC00D30

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#define DMA4_CURR_Y_COUNT 0xFFC00D38

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#define DMA5_NEXT_DESC_PTR 0xFFC00D40

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#define DMA5_START_ADDR 0xFFC00D44

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#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */

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#define DMA5_X_COUNT 0xFFC00D50

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#define DMA5_X_MODIFY 0xFFC00D54

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#define DMA5_Y_COUNT 0xFFC00D58

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#define DMA5_Y_MODIFY 0xFFC00D5C

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#define DMA5_CURR_DESC_PTR 0xFFC00D60

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#define DMA5_CURR_ADDR 0xFFC00D64

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#define DMA5_IRQ_STATUS 0xFFC00D68

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#define DMA5_PERIPHERAL_MAP 0xFFC00D6C

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#define DMA5_CURR_X_COUNT 0xFFC00D70

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#define DMA5_CURR_Y_COUNT 0xFFC00D78

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#define DMA6_NEXT_DESC_PTR 0xFFC00D80

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#define DMA6_START_ADDR 0xFFC00D84

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#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */

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#define DMA6_X_COUNT 0xFFC00D90

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#define DMA6_X_MODIFY 0xFFC00D94

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#define DMA6_Y_COUNT 0xFFC00D98

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#define DMA6_Y_MODIFY 0xFFC00D9C

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#define DMA6_CURR_DESC_PTR 0xFFC00DA0

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#define DMA6_CURR_ADDR 0xFFC00DA4

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#define DMA6_IRQ_STATUS 0xFFC00DA8

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#define DMA6_PERIPHERAL_MAP 0xFFC00DAC

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#define DMA6_CURR_X_COUNT 0xFFC00DB0

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#define DMA6_CURR_Y_COUNT 0xFFC00DB8

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#define DMA7_NEXT_DESC_PTR 0xFFC00DC0

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#define DMA7_START_ADDR 0xFFC00DC4

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#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */

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#define DMA7_X_COUNT 0xFFC00DD0

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#define DMA7_X_MODIFY 0xFFC00DD4

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#define DMA7_Y_COUNT 0xFFC00DD8

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#define DMA7_Y_MODIFY 0xFFC00DDC

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#define DMA7_CURR_DESC_PTR 0xFFC00DE0

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#define DMA7_CURR_ADDR 0xFFC00DE4

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#define DMA7_IRQ_STATUS 0xFFC00DE8

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#define DMA7_PERIPHERAL_MAP 0xFFC00DEC

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#define DMA7_CURR_X_COUNT 0xFFC00DF0

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#define DMA7_CURR_Y_COUNT 0xFFC00DF8

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#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00

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#define MDMA_D0_START_ADDR 0xFFC00E04

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#define MDMA_D0_CONFIG 0xFFC00E08

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#define MDMA_D0_X_COUNT 0xFFC00E10

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#define MDMA_D0_X_MODIFY 0xFFC00E14

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#define MDMA_D0_Y_COUNT 0xFFC00E18

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#define MDMA_D0_Y_MODIFY 0xFFC00E1C

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#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20

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#define MDMA_D0_CURR_ADDR 0xFFC00E24

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#define MDMA_D0_IRQ_STATUS 0xFFC00E28

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#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C

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#define MDMA_D0_CURR_X_COUNT 0xFFC00E30

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#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38

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#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40

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#define MDMA_S0_START_ADDR 0xFFC00E44

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#define MDMA_S0_CONFIG 0xFFC00E48

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#define MDMA_S0_X_COUNT 0xFFC00E50

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#define MDMA_S0_X_MODIFY 0xFFC00E54

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#define MDMA_S0_Y_COUNT 0xFFC00E58

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#define MDMA_S0_Y_MODIFY 0xFFC00E5C

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#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60

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#define MDMA_S0_CURR_ADDR 0xFFC00E64

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#define MDMA_S0_IRQ_STATUS 0xFFC00E68

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#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C

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#define MDMA_S0_CURR_X_COUNT 0xFFC00E70

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#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78

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#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80

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#define MDMA_D1_START_ADDR 0xFFC00E84

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#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */

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#define MDMA_D1_X_COUNT 0xFFC00E90

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#define MDMA_D1_X_MODIFY 0xFFC00E94

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#define MDMA_D1_Y_COUNT 0xFFC00E98

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#define MDMA_D1_Y_MODIFY 0xFFC00E9C

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#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0

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#define MDMA_D1_CURR_ADDR 0xFFC00EA4

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#define MDMA_D1_IRQ_STATUS 0xFFC00EA8

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#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC

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#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0

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#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8

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#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0

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#define MDMA_S1_START_ADDR 0xFFC00EC4

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#define MDMA_S1_CONFIG 0xFFC00EC8

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#define MDMA_S1_X_COUNT 0xFFC00ED0

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#define MDMA_S1_X_MODIFY 0xFFC00ED4

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#define MDMA_S1_Y_COUNT 0xFFC00ED8

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#define MDMA_S1_Y_MODIFY 0xFFC00EDC

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#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0

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#define MDMA_S1_CURR_ADDR 0xFFC00EE4

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#define MDMA_S1_IRQ_STATUS 0xFFC00EE8

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#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC

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#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0

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#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8

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#define EBIU_AMGCTL 0xFFC00A00

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#define EBIU_AMBCTL0 0xFFC00A04

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#define EBIU_AMBCTL1 0xFFC00A08

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#define EBIU_SDGCTL 0xFFC00A10

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#define EBIU_SDBCTL 0xFFC00A14

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#define EBIU_SDRRC 0xFFC00A18

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#define EBIU_SDSTAT 0xFFC00A1C

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#define DMA_TC_CNT 0xFFC00B0C

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#define DMA_TC_PER 0xFFC00B10

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2008-02-04 19:26:55 -0500

[diff] [blame]

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Mike Frysinger

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2010-07-26 01:06:37 -0400

[diff] [blame]

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#ifndef __BFIN_DEF_ADSP_BF533_proc__

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[diff] [blame]

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#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */

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#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)

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#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)

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2010-07-26 01:06:37 -0400

[diff] [blame]

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#endif

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[diff] [blame]

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#endif /* __BFIN_DEF_ADSP_BF531_proc__ */