wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Support for indirect PCI bridges. |
| 3 | * |
| 4 | * Copyright (C) 1998 Gabriel Paubert. |
| 5 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | |
Michael Schwingen | b9de2fa | 2011-05-23 00:00:12 +0200 | [diff] [blame] | 11 | #if !defined(__I386__) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 12 | |
| 13 | #include <asm/processor.h> |
| 14 | #include <asm/io.h> |
| 15 | #include <pci.h> |
| 16 | |
| 17 | #define cfg_read(val, addr, type, op) *val = op((type)(addr)) |
| 18 | #define cfg_write(val, addr, type, op) op((type *)(addr), (val)) |
| 19 | |
wdenk | bf2f8c9 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 20 | #if defined(CONFIG_MPC8260) |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 21 | #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ |
| 22 | static int \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 23 | indirect_##rw##_config_##size(struct pci_controller *hose, \ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 24 | pci_dev_t dev, int offset, type val) \ |
| 25 | { \ |
Kumar Gala | 233b992 | 2006-01-12 15:30:24 -0600 | [diff] [blame] | 26 | u32 b, d,f; \ |
| 27 | b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ |
| 28 | b = b - hose->first_busno; \ |
| 29 | dev = PCI_BDF(b, d, f); \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 30 | out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 31 | sync(); \ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 32 | cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 33 | return 0; \ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 34 | } |
Ed Swarthout | 09489ff | 2007-07-11 14:52:01 -0500 | [diff] [blame] | 35 | #elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 36 | #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ |
| 37 | static int \ |
| 38 | indirect_##rw##_config_##size(struct pci_controller *hose, \ |
| 39 | pci_dev_t dev, int offset, type val) \ |
| 40 | { \ |
Kumar Gala | 233b992 | 2006-01-12 15:30:24 -0600 | [diff] [blame] | 41 | u32 b, d,f; \ |
| 42 | b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ |
| 43 | b = b - hose->first_busno; \ |
| 44 | dev = PCI_BDF(b, d, f); \ |
Ed Swarthout | 09489ff | 2007-07-11 14:52:01 -0500 | [diff] [blame] | 45 | *(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \ |
wdenk | 9c53f40 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 46 | sync(); \ |
| 47 | cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ |
| 48 | return 0; \ |
| 49 | } |
Felix Radensky | bcaaeb8 | 2010-01-23 01:35:24 +0200 | [diff] [blame] | 50 | #elif defined(CONFIG_440GX) || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \ |
| 51 | defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT) |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 52 | #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ |
| 53 | static int \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 54 | indirect_##rw##_config_##size(struct pci_controller *hose, \ |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 55 | pci_dev_t dev, int offset, type val) \ |
| 56 | { \ |
Kumar Gala | 233b992 | 2006-01-12 15:30:24 -0600 | [diff] [blame] | 57 | u32 b, d,f; \ |
| 58 | b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ |
| 59 | b = b - hose->first_busno; \ |
| 60 | dev = PCI_BDF(b, d, f); \ |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 61 | if (PCI_BUS(dev) > 0) \ |
| 62 | out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \ |
| 63 | else \ |
| 64 | out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ |
| 65 | cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 66 | return 0; \ |
wdenk | 56ed43e | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 67 | } |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 68 | #else |
| 69 | #define INDIRECT_PCI_OP(rw, size, type, op, mask) \ |
| 70 | static int \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 71 | indirect_##rw##_config_##size(struct pci_controller *hose, \ |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 72 | pci_dev_t dev, int offset, type val) \ |
| 73 | { \ |
Kumar Gala | 233b992 | 2006-01-12 15:30:24 -0600 | [diff] [blame] | 74 | u32 b, d,f; \ |
| 75 | b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \ |
| 76 | b = b - hose->first_busno; \ |
| 77 | dev = PCI_BDF(b, d, f); \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 78 | out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 79 | cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 80 | return 0; \ |
wdenk | 2853603 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 81 | } |
| 82 | #endif |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 83 | |
| 84 | #define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask) \ |
| 85 | static int \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 86 | indirect_##rw##_config_##size(struct pci_controller *hose, \ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 87 | pci_dev_t dev, int offset, type val) \ |
| 88 | { \ |
| 89 | unsigned int msr = mfmsr(); \ |
| 90 | mtmsr(msr & ~(MSR_EE | MSR_CE)); \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 91 | out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 92 | cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 93 | out_le32(hose->cfg_addr, 0x00000000); \ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 94 | mtmsr(msr); \ |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 95 | return 0; \ |
wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3) |
| 99 | INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2) |
| 100 | INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0) |
| 101 | #ifdef CONFIG_405GP |
| 102 | INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3) |
| 103 | INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2) |
| 104 | INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0) |
| 105 | #else |
| 106 | INDIRECT_PCI_OP(write, byte, u8, out_8, 3) |
| 107 | INDIRECT_PCI_OP(write, word, u16, out_le16, 2) |
| 108 | INDIRECT_PCI_OP(write, dword, u32, out_le32, 0) |
| 109 | #endif |
| 110 | |
| 111 | void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data) |
| 112 | { |
| 113 | pci_set_ops(hose, |
| 114 | indirect_read_config_byte, |
| 115 | indirect_read_config_word, |
| 116 | indirect_read_config_dword, |
| 117 | indirect_write_config_byte, |
| 118 | indirect_write_config_word, |
| 119 | indirect_write_config_dword); |
| 120 | |
| 121 | hose->cfg_addr = (unsigned int *) cfg_addr; |
| 122 | hose->cfg_data = (unsigned char *) cfg_data; |
| 123 | } |
| 124 | |
Michael Schwingen | b9de2fa | 2011-05-23 00:00:12 +0200 | [diff] [blame] | 125 | #endif /* !__I386__ */ |