| Simon Glass | ec1a30c | 2019-12-06 21:41:43 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright 2019 Google LLC |
| 4 | */ |
| 5 | |
| Simon Glass | ec1a30c | 2019-12-06 21:41:43 -0700 | [diff] [blame] | 6 | #include <asm/io.h> |
| 7 | #include <asm/cpu_common.h> |
| 8 | #include <asm/fast_spi.h> |
| 9 | #include <asm/pci.h> |
| 10 | |
| 11 | /* |
| 12 | * Returns bios_start and fills in size of the BIOS region. |
| 13 | */ |
| 14 | static ulong fast_spi_get_bios_region(struct fast_spi_regs *regs, |
| 15 | uint *bios_size) |
| 16 | { |
| 17 | ulong bios_start, bios_end; |
| 18 | |
| 19 | /* |
| 20 | * BIOS_BFPREG provides info about BIOS-Flash Primary Region Base and |
| 21 | * Limit. Base and Limit fields are in units of 4K. |
| 22 | */ |
| 23 | u32 val = readl(®s->bfp); |
| 24 | |
| 25 | bios_start = (val & SPIBAR_BFPREG_PRB_MASK) << 12; |
| 26 | bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> |
| 27 | SPIBAR_BFPREG_PRL_SHIFT) + 1) << 12; |
| 28 | *bios_size = bios_end - bios_start; |
| 29 | |
| 30 | return bios_start; |
| 31 | } |
| 32 | |
| Simon Glass | 6c7799b | 2020-05-27 06:58:46 -0600 | [diff] [blame] | 33 | int fast_spi_get_bios_mmap_regs(struct fast_spi_regs *regs, ulong *map_basep, |
| 34 | uint *map_sizep, uint *offsetp) |
| 35 | { |
| 36 | ulong base; |
| 37 | |
| 38 | base = fast_spi_get_bios_region(regs, map_sizep); |
| 39 | *map_basep = (u32)-*map_sizep - base; |
| 40 | *offsetp = base; |
| 41 | |
| 42 | return 0; |
| 43 | } |
| 44 | |
| Simon Glass | ec1a30c | 2019-12-06 21:41:43 -0700 | [diff] [blame] | 45 | int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep, |
| 46 | uint *offsetp) |
| 47 | { |
| 48 | struct fast_spi_regs *regs; |
| Simon Glass | 6c7799b | 2020-05-27 06:58:46 -0600 | [diff] [blame] | 49 | ulong bar, mmio_base; |
| Simon Glass | ec1a30c | 2019-12-06 21:41:43 -0700 | [diff] [blame] | 50 | |
| 51 | /* Special case to find mapping without probing the device */ |
| 52 | pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32); |
| 53 | mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK; |
| 54 | regs = (struct fast_spi_regs *)mmio_base; |
| Simon Glass | ec1a30c | 2019-12-06 21:41:43 -0700 | [diff] [blame] | 55 | |
| Simon Glass | 6c7799b | 2020-05-27 06:58:46 -0600 | [diff] [blame] | 56 | return fast_spi_get_bios_mmap_regs(regs, map_basep, map_sizep, offsetp); |
| Simon Glass | ec1a30c | 2019-12-06 21:41:43 -0700 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base) |
| 60 | { |
| 61 | /* Program Temporary BAR for SPI */ |
| 62 | pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, |
| 63 | mmio_base | PCI_BASE_ADDRESS_SPACE_MEMORY, |
| 64 | PCI_SIZE_32); |
| 65 | |
| 66 | /* Enable Bus Master and MMIO Space */ |
| 67 | pci_x86_clrset_config(pdev, PCI_COMMAND, 0, PCI_COMMAND_MASTER | |
| 68 | PCI_COMMAND_MEMORY, PCI_SIZE_8); |
| 69 | |
| 70 | /* |
| 71 | * Disable the BIOS write protect so write commands are allowed. |
| 72 | * Enable Prefetching and caching. |
| 73 | */ |
| 74 | pci_x86_clrset_config(pdev, SPIBAR_BIOS_CONTROL, |
| 75 | SPIBAR_BIOS_CONTROL_EISS | |
| 76 | SPIBAR_BIOS_CONTROL_CACHE_DISABLE, |
| 77 | SPIBAR_BIOS_CONTROL_WPD | |
| 78 | SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE, PCI_SIZE_8); |
| 79 | |
| 80 | return 0; |
| 81 | } |