| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | |||||
| 3 | / { | ||||
| 4 | cpus { | ||||
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 5 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 6 | CPU0: cpu@0 { |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 7 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 8 | CPU0_intc: interrupt-controller { |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 9 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 10 | }; |
| 11 | }; | ||||
| 12 | CPU1: cpu@1 { | ||||
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 13 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 14 | CPU1_intc: interrupt-controller { |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 15 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 16 | }; |
| 17 | }; | ||||
| 18 | CPU2: cpu@2 { | ||||
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 19 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 20 | CPU2_intc: interrupt-controller { |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 21 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 22 | }; |
| 23 | }; | ||||
| 24 | CPU3: cpu@3 { | ||||
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 25 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 26 | CPU3_intc: interrupt-controller { |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 27 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 28 | }; |
| 29 | }; | ||||
| 30 | }; | ||||
| 31 | |||||
| 32 | memory@0 { | ||||
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 33 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 34 | }; |
| 35 | |||||
| 36 | soc { | ||||
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 37 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 38 | |
| Yu Chien Peter Lin | 739cd6f | 2022-10-25 23:03:50 +0800 | [diff] [blame] | 39 | plicsw: interrupt-controller@e6400000 { |
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 40 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 41 | }; |
| 42 | |||||
| 43 | plmt0@e6000000 { | ||||
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 44 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 45 | }; |
| 46 | }; | ||||
| 47 | |||||
| 48 | serial0: serial@f0300000 { | ||||
| Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 49 | bootph-pre-ram; |
| Bin Meng | 2114b47 | 2021-06-04 13:51:13 +0800 | [diff] [blame] | 50 | }; |
| 51 | |||||
| 52 | }; | ||||