Philippe Reynes | 3da5fb4 | 2018-10-11 18:31:59 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <fdtdec.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 8 | #include <init.h> |
Philippe Reynes | 3da5fb4 | 2018-10-11 18:31:59 +0200 | [diff] [blame] | 9 | #include <linux/io.h> |
| 10 | |
| 11 | #ifdef CONFIG_ARM64 |
| 12 | #include <asm/armv8/mmu.h> |
| 13 | |
| 14 | static struct mm_region broadcom_bcm968580xref_mem_map[] = { |
| 15 | { |
| 16 | /* RAM */ |
| 17 | .virt = 0x00000000UL, |
| 18 | .phys = 0x00000000UL, |
| 19 | .size = 8UL * SZ_1G, |
| 20 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 21 | PTE_BLOCK_INNER_SHARE |
| 22 | }, { |
| 23 | /* SoC */ |
| 24 | .virt = 0x80000000UL, |
| 25 | .phys = 0x80000000UL, |
| 26 | .size = 0xff80000000UL, |
| 27 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 28 | PTE_BLOCK_NON_SHARE | |
| 29 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 30 | }, { |
| 31 | /* List terminator */ |
| 32 | 0, |
| 33 | } |
| 34 | }; |
| 35 | |
| 36 | struct mm_region *mem_map = broadcom_bcm968580xref_mem_map; |
| 37 | #endif |
| 38 | |
| 39 | int board_init(void) |
| 40 | { |
| 41 | return 0; |
| 42 | } |
| 43 | |
| 44 | int dram_init(void) |
| 45 | { |
| 46 | if (fdtdec_setup_mem_size_base() != 0) |
| 47 | printf("fdtdec_setup_mem_size_base() has failed\n"); |
| 48 | |
| 49 | return 0; |
| 50 | } |
| 51 | |
| 52 | int dram_init_banksize(void) |
| 53 | { |
| 54 | fdtdec_setup_memory_banksize(); |
| 55 | |
| 56 | return 0; |
| 57 | } |
| 58 | |
| 59 | int print_cpuinfo(void) |
| 60 | { |
| 61 | return 0; |
| 62 | } |