Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 10164c674d8e1f133a2ee54218587ace0ee5550d / . / include / configs / CPU87.h
blob: 0e0876f807d58e95ab6a0589121bf8c12443592a [file] [log] [blame]
wdenk6d3c6d12005-04-03 22:35:21 +0000[diff] [blame]1/*
2 * (C) Copyright 2001-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_CPU87 1 /* ...on a CPU87 board */
38#define CONFIG_PCI
39
40/*
41 * select serial console configuration
42 *
43 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
44 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
45 * for SCC).
46 *
47 * if CONFIG_CONS_NONE is defined, then the serial console routines must
48 * defined elsewhere (for example, on the cogent platform, there are serial
49 * ports on the motherboard which are used for the serial console - see
50 * cogent/cma101/serial.[ch]).
51 */
52#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
53#define CONFIG_CONS_ON_SCC /* define if console on SCC */
54#undef CONFIG_CONS_NONE /* define if console on something else*/
55#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
56
57#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
58#define CONFIG_BAUDRATE 230400
59#else
60#define CONFIG_BAUDRATE 9600
61#endif
62
63/*
64 * select ethernet configuration
65 *
66 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
67 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
68 * for FCC)
69 *
70 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
71 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
72 * from CONFIG_COMMANDS to remove support for networking.
73 *
74 */
75#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
76#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
77#undef CONFIG_ETHER_NONE /* define if ether on something else */
78#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
79
80#define CONFIG_HAS_ETH1 1
81#define CONFIG_HAS_ETH2 1
82
83#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
84
85/*
86 * - Rx-CLK is CLK11
87 * - Tx-CLK is CLK12
88 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
89 * - Enable Full Duplex in FSMR
90 */
91# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
92# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
93# define CFG_CPMFCR_RAMTYPE 0
94# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
95
96#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
97
98/*
99 * - Rx-CLK is CLK13
100 * - Tx-CLK is CLK14
101 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
102 * - Enable Full Duplex in FSMR
103 */
104# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
105# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
106# define CFG_CPMFCR_RAMTYPE 0
107# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
108
109#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
110
111/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
112#define CONFIG_8260_CLKIN 100000000 /* in Hz */
113
114#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
115
wdenk6d3c6d12005-04-03 22:35:21 +0000[diff] [blame]116#define CONFIG_PREBOOT \
117 "echo; " \
118 "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
119 "echo"
120
121#undef CONFIG_BOOTARGS
122#define CONFIG_BOOTCOMMAND \
123 "bootp; " \
124 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
125 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
126 "bootm"
127
128/*-----------------------------------------------------------------------
129 * I2C/EEPROM/RTC configuration
130 */
131#define CONFIG_SOFT_I2C /* Software I2C support enabled */
132
133# define CFG_I2C_SPEED 50000
134# define CFG_I2C_SLAVE 0xFE
135/*
136 * Software (bit-bang) I2C driver configuration
137 */
138#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
139#define I2C_ACTIVE (iop->pdir |= 0x00010000)
140#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
141#define I2C_READ ((iop->pdat & 0x00010000) != 0)
142#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
143 else iop->pdat &= ~0x00010000
144#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
145 else iop->pdat &= ~0x00020000
146#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
147
148#define CONFIG_RTC_PCF8563
149#define CFG_I2C_RTC_ADDR 0x51
150
151#undef CONFIG_WATCHDOG /* watchdog disabled */
152
153/*-----------------------------------------------------------------------
154 * Disk-On-Chip configuration
155 */
156
157#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
158
159#define CFG_DOC_SUPPORT_2000
160#define CFG_DOC_SUPPORT_MILLENNIUM
161
162/*-----------------------------------------------------------------------
163 * Miscellaneous configuration options
164 */
165
166#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
167#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
168
169#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
170
171#ifdef CONFIG_PCI
172#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
173 CFG_CMD_BEDBUG | \
174 CFG_CMD_DATE | \
175 CFG_CMD_DOC | \
176 CFG_CMD_EEPROM | \
177 CFG_CMD_I2C | \
178 CFG_CMD_PCI)
179#else /* ! PCI */
180#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
181 CFG_CMD_BEDBUG | \
182 CFG_CMD_DATE | \
183 CFG_CMD_DOC | \
184 CFG_CMD_EEPROM | \
185 CFG_CMD_I2C )
186#endif /* CONFIG_PCI */
187
188/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
189#include <cmd_confdefs.h>
190
191/*
192 * Miscellaneous configurable options
193 */
194#define CFG_LONGHELP /* undef to save memory */
195#define CFG_PROMPT "=> " /* Monitor Command Prompt */
196#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
197#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
198#else
199#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
200#endif
201#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
202#define CFG_MAXARGS 16 /* max number of command args */
203#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
204
205#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
206#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
207
208#define CFG_LOAD_ADDR 0x100000 /* default load address */
209
210#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
211
212#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
213
214#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
215
216#define CONFIG_LOOPW
217
218/*
219 * For booting Linux, the board info and command line data
220 * have to be in the first 8 MB of memory, since this is
221 * the maximum mapped by the Linux kernel during initialization.
222 */
223#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
224
225/*-----------------------------------------------------------------------
226 * Flash configuration
227 */
228
229#define CFG_BOOTROM_BASE 0xFF800000
230#define CFG_BOOTROM_SIZE 0x00080000
231#define CFG_FLASH_BASE 0xFF000000
232#define CFG_FLASH_SIZE 0x00800000
233
234/*-----------------------------------------------------------------------
235 * FLASH organization
236 */
237#define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
238#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
239
240#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
241#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
242
243/*-----------------------------------------------------------------------
244 * Other areas to be mapped
245 */
246
247/* CS3: Dual ported SRAM */
248#define CFG_DPSRAM_BASE 0x40000000
249#define CFG_DPSRAM_SIZE 0x00100000
250
251/* CS4: DiskOnChip */
252#define CFG_DOC_BASE 0xF4000000
253#define CFG_DOC_SIZE 0x00100000
254
255/* CS5: FDC37C78 controller */
256#define CFG_FDC37C78_BASE 0xF1000000
257#define CFG_FDC37C78_SIZE 0x00100000
258
259/* CS6: Board configuration registers */
260#define CFG_BCRS_BASE 0xF2000000
261#define CFG_BCRS_SIZE 0x00010000
262
263/* CS7: VME Extended Access Range */
264#define CFG_VMEEAR_BASE 0x60000000
265#define CFG_VMEEAR_SIZE 0x01000000
266
267/* CS8: VME Standard Access Range */
268#define CFG_VMESAR_BASE 0xFE000000
269#define CFG_VMESAR_SIZE 0x01000000
270
271/* CS9: VME Short I/O Access Range */
272#define CFG_VMESIOAR_BASE 0xFD000000
273#define CFG_VMESIOAR_SIZE 0x01000000
274
275/*-----------------------------------------------------------------------
276 * Hard Reset Configuration Words
277 *
278 * if you change bits in the HRCW, you must also change the CFG_*
279 * defines for the various registers affected by the HRCW e.g. changing
280 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
281 */
282#if defined(CONFIG_BOOT_ROM)
283#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
284 HRCW_BPS01 | HRCW_CS10PC01)
285#else
286#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
287#endif
288
289/* no slaves so just fill with zeros */
290#define CFG_HRCW_SLAVE1 0
291#define CFG_HRCW_SLAVE2 0
292#define CFG_HRCW_SLAVE3 0
293#define CFG_HRCW_SLAVE4 0
294#define CFG_HRCW_SLAVE5 0
295#define CFG_HRCW_SLAVE6 0
296#define CFG_HRCW_SLAVE7 0
297
298/*-----------------------------------------------------------------------
299 * Internal Memory Mapped Register
300 */
301#define CFG_IMMR 0xF0000000
302
303/*-----------------------------------------------------------------------
304 * Definitions for initial stack pointer and data area (in DPRAM)
305 */
306#define CFG_INIT_RAM_ADDR CFG_IMMR
307#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
308#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
309#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
310#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
311
312/*-----------------------------------------------------------------------
313 * Start addresses for the final memory configuration
314 * (Set up by the startup code)
315 * Please note that CFG_SDRAM_BASE _must_ start at 0
316 *
317 * 60x SDRAM is mapped at CFG_SDRAM_BASE.
318 */
319#define CFG_SDRAM_BASE 0x00000000
320#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
321#define CFG_MONITOR_BASE TEXT_BASE
322#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
323#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
324
325#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
326# define CFG_RAMBOOT
327#endif
328
329#ifdef CONFIG_PCI
330#define CONFIG_PCI_PNP
331#define CONFIG_EEPRO100
332#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
333#endif
334
335#if 0
336/* environment is in Flash */
337#define CFG_ENV_IS_IN_FLASH 1
338#ifdef CONFIG_BOOT_ROM
339# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000)
340# define CFG_ENV_SIZE 0x10000
341# define CFG_ENV_SECT_SIZE 0x10000
342#endif
343#else
344/* environment is in EEPROM */
345#define CFG_ENV_IS_IN_EEPROM 1
346#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
347#define CFG_I2C_EEPROM_ADDR_LEN 1
348/* mask of address bits that overflow into the "EEPROM chip address" */
349#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
350#define CFG_EEPROM_PAGE_WRITE_BITS 4
351#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
352#define CFG_ENV_OFFSET 512
353#define CFG_ENV_SIZE (2048 - 512)
354#endif
355
356/*
357 * Internal Definitions
358 *
359 * Boot Flags
360 */
361#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
362#define BOOTFLAG_WARM 0x02 /* Software reboot */
363
364
365/*-----------------------------------------------------------------------
366 * Cache Configuration
367 */
368#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
369#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
370# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
371#endif
372
373/*-----------------------------------------------------------------------
374 * HIDx - Hardware Implementation-dependent Registers 2-11
375 *-----------------------------------------------------------------------
376 * HID0 also contains cache control - initially enable both caches and
377 * invalidate contents, then the final state leaves only the instruction
378 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
379 * but Soft reset does not.
380 *
381 * HID1 has only read-only information - nothing to set.
382 */
383#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
384 HID0_DCI|HID0_IFEM|HID0_ABE)
385#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
386#define CFG_HID2 0
387
388/*-----------------------------------------------------------------------
389 * RMR - Reset Mode Register 5-5
390 *-----------------------------------------------------------------------
391 * turn on Checkstop Reset Enable
392 */
393#define CFG_RMR RMR_CSRE
394
395/*-----------------------------------------------------------------------
396 * BCR - Bus Configuration 4-25
397 *-----------------------------------------------------------------------
398 */
399#define BCR_APD01 0x10000000
400#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
401
402/*-----------------------------------------------------------------------
403 * SIUMCR - SIU Module Configuration 4-31
404 *-----------------------------------------------------------------------
405 */
406#define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
407 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
408
409/*-----------------------------------------------------------------------
410 * SYPCR - System Protection Control 4-35
411 * SYPCR can only be written once after reset!
412 *-----------------------------------------------------------------------
413 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
414 */
415#if defined(CONFIG_WATCHDOG)
416#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
417 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
418#else
419#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
420 SYPCR_SWRI|SYPCR_SWP)
421#endif /* CONFIG_WATCHDOG */
422
423/*-----------------------------------------------------------------------
424 * TMCNTSC - Time Counter Status and Control 4-40
425 *-----------------------------------------------------------------------
426 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
427 * and enable Time Counter
428 */
429#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
430
431/*-----------------------------------------------------------------------
432 * PISCR - Periodic Interrupt Status and Control 4-42
433 *-----------------------------------------------------------------------
434 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
435 * Periodic timer
436 */
437#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
438
439/*-----------------------------------------------------------------------
440 * SCCR - System Clock Control 9-8
441 *-----------------------------------------------------------------------
442 * Ensure DFBRG is Divide by 16
443 */
444#define CFG_SCCR SCCR_DFBRG01
445
446/*-----------------------------------------------------------------------
447 * RCCR - RISC Controller Configuration 13-7
448 *-----------------------------------------------------------------------
449 */
450#define CFG_RCCR 0
451
452#define CFG_MIN_AM_MASK 0xC0000000
453
454/*
455 * we use the same values for 32 MB and 128 MB SDRAM
456 * refresh rate = 7.68 uS (100 MHz Bus Clock)
457 */
458
459/*-----------------------------------------------------------------------
460 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
461 *-----------------------------------------------------------------------
462 */
463#define CFG_MPTPR 0x2000
464
465/*-----------------------------------------------------------------------
466 * PSRT - Refresh Timer Register 10-16
467 *-----------------------------------------------------------------------
468 */
469#define CFG_PSRT 0x16
470
471/*-----------------------------------------------------------------------
472 * PSRT - SDRAM Mode Register 10-10
473 *-----------------------------------------------------------------------
474 */
475
476 /* SDRAM initialization values for 8-column chips
477 */
478#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
479 ORxS_BPD_4 |\
480 ORxS_ROWST_PBI0_A9 |\
481 ORxS_NUMR_12)
482
483#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
484 PSDMR_BSMA_A14_A16 |\
485 PSDMR_SDA10_PBI0_A10 |\
486 PSDMR_RFRC_7_CLK |\
487 PSDMR_PRETOACT_2W |\
488 PSDMR_ACTTORW_2W |\
489 PSDMR_LDOTOPRE_1C |\
490 PSDMR_WRC_1C |\
491 PSDMR_CL_2)
492
493 /* SDRAM initialization values for 9-column chips
494 */
495#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
496 ORxS_BPD_4 |\
497 ORxS_ROWST_PBI0_A7 |\
498 ORxS_NUMR_13)
499
500#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
501 PSDMR_BSMA_A13_A15 |\
502 PSDMR_SDA10_PBI0_A9 |\
503 PSDMR_RFRC_7_CLK |\
504 PSDMR_PRETOACT_2W |\
505 PSDMR_ACTTORW_2W |\
506 PSDMR_LDOTOPRE_1C |\
507 PSDMR_WRC_1C |\
508 PSDMR_CL_2)
509
510/*
511 * Init Memory Controller:
512 *
513 * Bank Bus Machine PortSz Device
514 * ---- --- ------- ------ ------
515 * 0 60x GPCM 8 bit Boot ROM
516 * 1 60x GPCM 64 bit FLASH
517 * 2 60x SDRAM 64 bit SDRAM
518 *
519 */
520
521#define CFG_MRS_OFFS 0x00000000
522
523#ifdef CONFIG_BOOT_ROM
524/* Bank 0 - Boot ROM
525 */
526#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
527 BRx_PS_8 |\
528 BRx_MS_GPCM_P |\
529 BRx_V)
530
531#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
532 ORxG_CSNT |\
533 ORxG_ACS_DIV1 |\
534 ORxG_SCY_5_CLK |\
535 ORxU_EHTR_8IDLE)
536
537/* Bank 1 - FLASH
538 */
539#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
540 BRx_PS_64 |\
541 BRx_MS_GPCM_P |\
542 BRx_V)
543
544#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
545 ORxG_CSNT |\
546 ORxG_ACS_DIV1 |\
547 ORxG_SCY_5_CLK |\
548 ORxU_EHTR_8IDLE)
549
550#else /* CONFIG_BOOT_ROM */
551/* Bank 0 - FLASH
552 */
553#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
554 BRx_PS_64 |\
555 BRx_MS_GPCM_P |\
556 BRx_V)
557
558#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
559 ORxG_CSNT |\
560 ORxG_ACS_DIV1 |\
561 ORxG_SCY_5_CLK |\
562 ORxU_EHTR_8IDLE)
563
564/* Bank 1 - Boot ROM
565 */
566#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
567 BRx_PS_8 |\
568 BRx_MS_GPCM_P |\
569 BRx_V)
570
571#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
572 ORxG_CSNT |\
573 ORxG_ACS_DIV1 |\
574 ORxG_SCY_5_CLK |\
575 ORxU_EHTR_8IDLE)
576
577#endif /* CONFIG_BOOT_ROM */
578
579
580/* Bank 2 - 60x bus SDRAM
581 */
582#ifndef CFG_RAMBOOT
583#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
584 BRx_PS_64 |\
585 BRx_MS_SDRAM_P |\
586 BRx_V)
587
588#define CFG_OR2_PRELIM CFG_OR2_9COL
589
590#define CFG_PSDMR CFG_PSDMR_9COL
591#endif /* CFG_RAMBOOT */
592
593/* Bank 3 - Dual Ported SRAM
594 */
595#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
596 BRx_PS_16 |\
597 BRx_MS_GPCM_P |\
598 BRx_V)
599
600#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\
601 ORxG_CSNT |\
602 ORxG_ACS_DIV1 |\
603 ORxG_SCY_7_CLK |\
604 ORxG_SETA)
605
606/* Bank 4 - DiskOnChip
607 */
608#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
609 BRx_PS_8 |\
610 BRx_MS_GPCM_P |\
611 BRx_V)
612
613#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
614 ORxG_CSNT |\
615 ORxG_ACS_DIV2 |\
616 ORxG_SCY_9_CLK |\
617 ORxU_EHTR_8IDLE)
618
619/* Bank 5 - FDC37C78 controller
620 */
621#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
622 BRx_PS_8 |\
623 BRx_MS_GPCM_P |\
624 BRx_V)
625
626#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\
627 ORxG_ACS_DIV2 |\
628 ORxG_SCY_10_CLK |\
629 ORxU_EHTR_8IDLE)
630
631/* Bank 6 - Board control registers
632 */
633#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\
634 BRx_PS_8 |\
635 BRx_MS_GPCM_P |\
636 BRx_V)
637
638#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\
639 ORxG_CSNT |\
640 ORxG_SCY_7_CLK)
641
642/* Bank 7 - VME Extended Access Range
643 */
644#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
645 BRx_PS_32 |\
646 BRx_MS_GPCM_P |\
647 BRx_V)
648
649#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\
650 ORxG_CSNT |\
651 ORxG_ACS_DIV1 |\
652 ORxG_SCY_7_CLK |\
653 ORxG_SETA)
654
655/* Bank 8 - VME Standard Access Range
656 */
657#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
658 BRx_PS_16 |\
659 BRx_MS_GPCM_P |\
660 BRx_V)
661
662#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\
663 ORxG_CSNT |\
664 ORxG_ACS_DIV1 |\
665 ORxG_SCY_7_CLK |\
666 ORxG_SETA)
667
668/* Bank 9 - VME Short I/O Access Range
669 */
670#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
671 BRx_PS_16 |\
672 BRx_MS_GPCM_P |\
673 BRx_V)
674
675#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\
676 ORxG_CSNT |\
677 ORxG_ACS_DIV1 |\
678 ORxG_SCY_7_CLK |\
679 ORxG_SETA)
680
681#endif /* __CONFIG_H */