blob: e48e20f6853f3d549fe85240dd4b092e9f81bb1f [file] [log] [blame]
wdenkda27dcf2002-09-10 19:19:06 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Rolf Offermanns <rof@sysgo.de>
5 *
6 * Configuation settings for the SSV DNP1110 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * If we are developing, we might want to start armboot from ram
32 * so we MUST NOT initialize critical regs like mem-timing ...
33 */
wdenk3d3d99f2005-04-04 12:44:11 +000034#define CONFIG_SKIP_LOWLEVEL_INIT 1
35#undef CONFIG_SKIP_RELOCATE_UBOOT
wdenkda27dcf2002-09-10 19:19:06 +000036
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41#define CONFIG_SA1110 1 /* This is an SA1110 CPU */
42#define CONFIG_DNP1110 1 /* on an DNP/1110 Board */
43
44#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020045/* we will never enable dcache, because we have to setup MMU first */
46#define CONFIG_SYS_NO_DCACHE
wdenkda27dcf2002-09-10 19:19:06 +000047
48/*
49 * Size of malloc() pool
50 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020051#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
52#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenkda27dcf2002-09-10 19:19:06 +000053
54/*
55 * Hardware drivers
56 */
Ben Warren0fd6aae2009-10-04 22:37:03 -070057#define CONFIG_NET_MULTI
58#define CONFIG_SMC91111
wdenkda27dcf2002-09-10 19:19:06 +000059#define CONFIG_SMC91111_BASE 0x20000300
60
61
62/*
63 * select serial console configuration
64 */
Jean-Christophe PLAGNIOL-VILLARD0b4c0642009-03-29 23:01:41 +020065#define CONFIG_SA1100_SERIAL
wdenkda27dcf2002-09-10 19:19:06 +000066#define CONFIG_SERIAL1 1 /* we use SERIAL 1 */
67
68/* allow to overwrite serial and ethaddr */
69#define CONFIG_ENV_OVERWRITE
70
71#define CONFIG_BAUDRATE 115200
72
wdenkda27dcf2002-09-10 19:19:06 +000073
Jon Loeligerb15a23b2007-07-04 22:32:03 -050074/*
Jon Loeligere54e77a2007-07-10 09:29:01 -050075 * BOOTP options
76 */
77#define CONFIG_BOOTP_BOOTFILESIZE
78#define CONFIG_BOOTP_BOOTPATH
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81
82
83/*
Jon Loeligerb15a23b2007-07-04 22:32:03 -050084 * Command line configuration.
85 */
86#include <config_cmd_default.h>
87
wdenkda27dcf2002-09-10 19:19:06 +000088
89#define CONFIG_BOOTDELAY 3
Wolfgang Denka1be4762008-05-20 16:00:29 +020090#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200"
wdenkda27dcf2002-09-10 19:19:06 +000091#define CONFIG_ETHADDR 02:80:ad:20:31:b8
92#define CONFIG_NETMASK 255.255.0.0
93#define CONFIG_IPADDR 172.22.2.23
94#define CONFIG_SERVERIP 172.22.2.22
wdenkc8434db2003-03-26 06:55:25 +000095#define CONFIG_BOOTFILE "dnp1110"
wdenkda27dcf2002-09-10 19:19:06 +000096#define CONFIG_BOOTCOMMAND "tftp; bootm"
97
Jon Loeligerb15a23b2007-07-04 22:32:03 -050098#if defined(CONFIG_CMD_KGDB)
wdenkda27dcf2002-09-10 19:19:06 +000099#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
100#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
101#endif
102
103/*
104 * Miscellaneous configurable options
105 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200106#define CONFIG_SYS_LONGHELP /* undef to save memory */
107#define CONFIG_SYS_PROMPT "DNP1110 # " /* Monitor Command Prompt */
108#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
109#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
110#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
111#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkda27dcf2002-09-10 19:19:06 +0000112
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200113#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */
114#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
wdenkda27dcf2002-09-10 19:19:06 +0000115
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200116#define CONFIG_SYS_LOAD_ADDR 0xc0200000 /* default load address */
wdenkda27dcf2002-09-10 19:19:06 +0000117
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200118#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
119#define CONFIG_SYS_CPUSPEED 0x0b /* set core clock to 220 MHz */
wdenkda27dcf2002-09-10 19:19:06 +0000120
121 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkda27dcf2002-09-10 19:19:06 +0000123
124/*-----------------------------------------------------------------------
125 * Stack sizes
126 *
127 * The stack sizes are set up in start.S using the settings below
128 */
129#define CONFIG_STACKSIZE (128*1024) /* regular stack */
130#ifdef CONFIG_USE_IRQ
131#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
132#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
133#endif
134
135/*-----------------------------------------------------------------------
136 * Physical Memory Map
137 */
138#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
139#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
140#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
141
142
143#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
144#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
wdenkc8434db2003-03-26 06:55:25 +0000145#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 32 MB Banks */
146#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
wdenkda27dcf2002-09-10 19:19:06 +0000147
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkda27dcf2002-09-10 19:19:06 +0000149
150/*-----------------------------------------------------------------------
151 * FLASH and environment organization
152 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200153#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
154#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkda27dcf2002-09-10 19:19:06 +0000155
156/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200157#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
158#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkda27dcf2002-09-10 19:19:06 +0000159
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200160#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200161#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xF80000) /* Addr of Environment Sector */
162#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkda27dcf2002-09-10 19:19:06 +0000163
164#endif /* __CONFIG_H */