| Lokesh Vutla | b50abe2 | 2018-11-02 19:51:09 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ |
| 4 | * This file was generated by the AM65x_DRA80xM EMIF Tool: |
| 5 | * http://www.ti.com/lit/pdf/spracj0 |
| 6 | * Configuration Parameters |
| 7 | * Memory Type: DDR4 |
| 8 | * Data Rate: 1600 |
| 9 | * ECC Enabled: No |
| 10 | * Data Width: 32 |
| 11 | */ |
| 12 | #define DDR_PLL_FREQUENCY 400000000 |
| 13 | #define DDRCTL_MSTR 0x41040010 |
| 14 | #define DDRCTL_RFSHCTL0 0x00210070 |
| 15 | #define DDRCTL_ECCCFG0 0x00000000 |
| 16 | #define DDRCTL_RFSHTMG 0x0061008C |
| 17 | #define DDRCTL_CRCPARCTL0 0x00008000 |
| 18 | #define DDRCTL_CRCPARCTL1 0x1A000000 |
| 19 | #define DDRCTL_CRCPARCTL2 0x0048051E |
| 20 | #define DDRCTL_INIT0 0x400100C4 |
| 21 | #define DDRCTL_INIT1 0x004F0000 |
| 22 | #define DDRCTL_INIT3 0x02140501 |
| 23 | #define DDRCTL_INIT4 0x00000020 |
| 24 | #define DDRCTL_INIT5 0x00100000 |
| 25 | #define DDRCTL_INIT6 0x00000480 |
| 26 | #define DDRCTL_INIT7 0x000004E8 |
| 27 | #define DDRCTL_DRAMTMG0 0x0C0A1B0D |
| 28 | #define DDRCTL_DRAMTMG1 0x00030313 |
| 29 | #define DDRCTL_DRAMTMG2 0x0506050A |
| 30 | #define DDRCTL_DRAMTMG3 0x0000400C |
| 31 | #define DDRCTL_DRAMTMG4 0x06020206 |
| 32 | #define DDRCTL_DRAMTMG5 0x04040302 |
| 33 | #define DDRCTL_DRAMTMG6 0x00000004 |
| 34 | #define DDRCTL_DRAMTMG7 0x00000404 |
| 35 | #define DDRCTL_DRAMTMG8 0x03030C05 |
| 36 | #define DDRCTL_DRAMTMG9 0x00020208 |
| 37 | #define DDRCTL_DRAMTMG10 0x001C180A |
| 38 | #define DDRCTL_DRAMTMG11 0x1106010E |
| 39 | #define DDRCTL_DRAMTMG12 0x00020008 |
| 40 | #define DDRCTL_DRAMTMG13 0x0B100002 |
| 41 | #define DDRCTL_DRAMTMG14 0x00000000 |
| 42 | #define DDRCTL_DRAMTMG15 0x0000003F |
| 43 | #define DDRCTL_DRAMTMG17 0x00500028 |
| 44 | #define DDRCTL_ZQCTL0 0x21000040 |
| 45 | #define DDRCTL_ZQCTL1 0x0202FAF0 |
| 46 | #define DDRCTL_DFITMG0 0x04888206 |
| 47 | #define DDRCTL_DFITMG1 0x000A0606 |
| 48 | #define DDRCTL_DFITMG2 0x00000604 |
| 49 | #define DDRCTL_DFIMISC 0x00000001 |
| 50 | #define DDRCTL_ADDRMAP0 0x001F1F1F |
| 51 | #define DDRCTL_ADDRMAP1 0x003F0808 |
| 52 | #define DDRCTL_ADDRMAP2 0x00000000 |
| 53 | #define DDRCTL_ADDRMAP3 0x00000000 |
| 54 | #define DDRCTL_ADDRMAP4 0x00001F1F |
| 55 | #define DDRCTL_ADDRMAP5 0x08080808 |
| 56 | #define DDRCTL_ADDRMAP6 0x08080808 |
| 57 | #define DDRCTL_ADDRMAP7 0x00000F0F |
| 58 | #define DDRCTL_ADDRMAP8 0x00000A0A |
| 59 | #define DDRCTL_ADDRMAP9 0x00000000 |
| 60 | #define DDRCTL_ADDRMAP10 0x00000000 |
| 61 | #define DDRCTL_ADDRMAP11 0x001F1F00 |
| 62 | #define DDRCTL_DQMAP0 0x00000000 |
| 63 | #define DDRCTL_DQMAP1 0x00000000 |
| 64 | #define DDRCTL_DQMAP4 0x00000000 |
| 65 | #define DDRCTL_DQMAP5 0x00000000 |
| 66 | #define DDRCTL_PWRCTL 0x00000000 |
| 67 | #define DDRCTL_RANKCTL 0x00000000 |
| 68 | #define DDRCTL_ODTCFG 0x0600060C |
| 69 | #define DDRCTL_ODTMAP 0x00000001 |
| 70 | #define DDRPHY_PGCR0 0x07001E00 |
| 71 | #define DDRPHY_PGCR1 0x020046C0 |
| 72 | #define DDRPHY_PGCR2 0x00F0BFE0 |
| 73 | #define DDRPHY_PGCR3 0x55AA0080 |
| 74 | #define DDRPHY_PGCR6 0x00013001 |
| 75 | #define DDRPHY_PTR2 0x00083DEF |
| 76 | #define DDRPHY_PTR3 0x00061A80 |
| 77 | #define DDRPHY_PTR4 0x00000120 |
| 78 | #define DDRPHY_PTR5 0x00027100 |
| 79 | #define DDRPHY_PTR6 0x04000320 |
| 80 | #define DDRPHY_PLLCR0 0x021c4000 |
| 81 | #define DDRPHY_DXCCR 0x00000038 |
| 82 | #define DDRPHY_DSGCR 0x02A0C129 |
| 83 | #define DDRPHY_DCR 0x0000040C |
| 84 | #define DDRPHY_DTPR0 0x041A0B06 |
| 85 | #define DDRPHY_DTPR1 0x28140000 |
| 86 | #define DDRPHY_DTPR2 0x0034E300 |
| 87 | #define DDRPHY_DTPR3 0x02800800 |
| 88 | #define DDRPHY_DTPR4 0x31180805 |
| 89 | #define DDRPHY_DTPR5 0x00250B06 |
| 90 | #define DDRPHY_DTPR6 0x00000505 |
| 91 | #define DDRPHY_ZQCR 0x008A2A58 |
| 92 | #define DDRPHY_ZQ0PR0 0x000077DD |
| 93 | #define DDRPHY_ZQ1PR0 0x000077DD |
| 94 | #define DDRPHY_MR0 0x00000214 |
| 95 | #define DDRPHY_MR1 0x00000501 |
| 96 | #define DDRPHY_MR2 0x00000000 |
| 97 | #define DDRPHY_MR3 0x00000020 |
| 98 | #define DDRPHY_MR4 0x00000000 |
| 99 | #define DDRPHY_MR5 0x00000480 |
| 100 | #define DDRPHY_MR6 0x000004E8 |
| 101 | #define DDRPHY_MR11 0x00000000 |
| 102 | #define DDRPHY_MR12 0x00000000 |
| 103 | #define DDRPHY_MR13 0x00000000 |
| 104 | #define DDRPHY_MR14 0x00000000 |
| 105 | #define DDRPHY_MR22 0x00000000 |
| 106 | #define DDRPHY_VTCR0 0xF3C32028 |
| 107 | #define DDRPHY_DX8SL0PLLCR0 0x021c4000 |
| 108 | #define DDRPHY_DX8SL1PLLCR0 0x021c4000 |
| 109 | #define DDRPHY_DX8SL2PLLCR0 0x021c4000 |
| 110 | #define DDRPHY_DTCR0 0x8000B1C7 |
| 111 | #define DDRPHY_DTCR1 0x00010236 |
| 112 | #define DDRPHY_ACIOCR5 0x04800000 |
| 113 | #define DDRPHY_IOVCR0 0x0F0C0C0C |
| 114 | #define DDRPHY_DX0GCR0 0x00000000 |
| 115 | #define DDRPHY_DX0GCR1 0x00000000 |
| 116 | #define DDRPHY_DX0GCR2 0x00000000 |
| 117 | #define DDRPHY_DX0GCR3 0x00000000 |
| 118 | #define DDRPHY_DX1GCR0 0x00000000 |
| 119 | #define DDRPHY_DX1GCR1 0x00000000 |
| 120 | #define DDRPHY_DX1GCR2 0x00000000 |
| 121 | #define DDRPHY_DX1GCR3 0x00000000 |
| 122 | #define DDRPHY_DX2GCR0 0x40700204 |
| 123 | #define DDRPHY_DX2GCR1 0x00007FFF |
| 124 | #define DDRPHY_DX2GCR2 0x00000000 |
| 125 | #define DDRPHY_DX2GCR3 0xFFC0010B |
| 126 | #define DDRPHY_DX3GCR0 0x40700204 |
| 127 | #define DDRPHY_DX3GCR1 0x00007FFF |
| 128 | #define DDRPHY_DX3GCR2 0x00000000 |
| 129 | #define DDRPHY_DX3GCR3 0xFFC0010B |
| 130 | #define DDRPHY_DX4GCR0 0x40703220 |
| 131 | #define DDRPHY_DX4GCR1 0x55556000 |
| 132 | #define DDRPHY_DX4GCR2 0xAAAA0000 |
| 133 | #define DDRPHY_DX4GCR3 0xFFE18587 |
| 134 | #define DDRPHY_DX0GCR4 0x0E00B03C |
| 135 | #define DDRPHY_DX1GCR4 0x0E00B03C |
| 136 | #define DDRPHY_DX2GCR4 0x0E00B03C |
| 137 | #define DDRPHY_DX3GCR4 0x0E00B03C |
| 138 | #define DDRPHY_DX4GCR4 0x0E00B03C |
| 139 | #define DDRPHY_PGCR5 0x01010004 |
| 140 | #define DDRPHY_DX0GCR5 0x00000049 |
| 141 | #define DDRPHY_DX1GCR5 0x00000049 |
| 142 | #define DDRPHY_DX2GCR5 0x00000049 |
| 143 | #define DDRPHY_DX3GCR5 0x00000049 |
| 144 | #define DDRPHY_DX4GCR5 0x00000049 |
| 145 | #define DDRPHY_DX0GTR0 0x00020002 |
| 146 | #define DDRPHY_DX1GTR0 0x00020002 |
| 147 | #define DDRPHY_DX2GTR0 0x00020002 |
| 148 | #define DDRPHY_DX3GTR0 0x00020002 |
| 149 | #define DDRPHY_DX4GTR0 0x00020002 |
| 150 | #define DDRPHY_ODTCR 0x00010000 |
| 151 | #define DDRPHY_DX8SL0IOCR 0x04800000 |
| 152 | #define DDRPHY_DX8SL1IOCR 0x04800000 |
| 153 | #define DDRPHY_DX8SL2IOCR 0x04800000 |
| 154 | #define DDRPHY_DX8SL0DXCTL2 0x00141830 |
| 155 | #define DDRPHY_DX8SL1DXCTL2 0x00141830 |
| 156 | #define DDRPHY_DX8SL2DXCTL2 0x00141830 |