Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 1 | /* |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 2 | * Copyright 2007-2012 Freescale Semiconductor, Inc. |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * p2020ds board configuration file |
| 25 | * |
| 26 | */ |
| 27 | #ifndef __CONFIG_H |
| 28 | #define __CONFIG_H |
| 29 | |
Kumar Gala | e47cc38 | 2010-05-21 03:02:16 -0500 | [diff] [blame] | 30 | #include "../board/freescale/common/ics307_clk.h" |
| 31 | |
Wolfgang Denk | dc25d15 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 32 | #ifdef CONFIG_36BIT |
Kumar Gala | 84de713 | 2009-09-10 16:26:37 -0500 | [diff] [blame] | 33 | #define CONFIG_PHYS_64BIT |
| 34 | #endif |
| 35 | |
Jerry Huang | 2c766ba | 2011-01-24 17:09:54 +0000 | [diff] [blame] | 36 | #ifdef CONFIG_SDCARD |
| 37 | #define CONFIG_SYS_RAMBOOT |
| 38 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 39 | #define CONFIG_SYS_TEXT_BASE 0xf8f80000 |
| 40 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
| 41 | #endif |
| 42 | |
Jerry Huang | 6326092 | 2011-01-24 17:09:56 +0000 | [diff] [blame] | 43 | #ifdef CONFIG_SPIFLASH |
| 44 | #define CONFIG_SYS_RAMBOOT |
| 45 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
| 46 | #define CONFIG_SYS_TEXT_BASE 0xf8f80000 |
| 47 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
| 48 | #endif |
| 49 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 50 | /* High Level Configuration Options */ |
| 51 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 52 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 53 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
| 54 | #define CONFIG_P2020 1 |
| 55 | #define CONFIG_P2020DS 1 |
| 56 | #define CONFIG_MP 1 /* support multiple processors */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 57 | |
Wolfgang Denk | 291ba1b | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 58 | #ifndef CONFIG_SYS_TEXT_BASE |
| 59 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 |
| 60 | #endif |
| 61 | |
Kumar Gala | e727a36 | 2011-01-12 02:48:53 -0600 | [diff] [blame] | 62 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
| 63 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
| 64 | #endif |
| 65 | |
Li Yang | 1f558db | 2010-12-30 11:17:44 -0600 | [diff] [blame] | 66 | #define CONFIG_SYS_SRIO |
| 67 | #define CONFIG_SRIO1 /* SRIO port 1 */ |
| 68 | #define CONFIG_SRIO2 /* SRIO port 2 */ |
| 69 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 70 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
| 71 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 72 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
| 73 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ |
| 74 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ |
| 75 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
| 76 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
| 77 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 78 | |
| 79 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
Roy Zang | e71921a | 2009-06-30 13:56:23 +0800 | [diff] [blame] | 80 | #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 81 | |
| 82 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 83 | #define CONFIG_ENV_OVERWRITE |
| 84 | |
Kumar Gala | e47cc38 | 2010-05-21 03:02:16 -0500 | [diff] [blame] | 85 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
| 86 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 87 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 88 | |
| 89 | /* |
| 90 | * These can be toggled for performance analysis, otherwise use default. |
| 91 | */ |
| 92 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 93 | #define CONFIG_BTB /* toggle branch predition */ |
| 94 | |
Jerry Huang | b0bd775 | 2011-01-24 17:09:53 +0000 | [diff] [blame] | 95 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ |
| 96 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 97 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 98 | |
| 99 | #ifdef CONFIG_PHYS_64BIT |
| 100 | #define CONFIG_ADDR_MAP 1 |
| 101 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| 102 | #endif |
| 103 | |
York Sun | 1443f36 | 2010-09-28 15:20:37 -0700 | [diff] [blame] | 104 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
| 105 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
| 106 | #define CONFIG_SYS_MEMTEST_END 0x00400000 |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 107 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 108 | |
| 109 | /* |
Jerry Huang | 2c766ba | 2011-01-24 17:09:54 +0000 | [diff] [blame] | 110 | * Config the L2 Cache |
| 111 | */ |
| 112 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 |
| 113 | #ifdef CONFIG_PHYS_64BIT |
| 114 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull |
| 115 | #else |
| 116 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR |
| 117 | #endif |
| 118 | #define CONFIG_SYS_L2_SIZE (512 << 10) |
| 119 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
| 120 | |
Timur Tabi | d8f341c | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 121 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
| 122 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 123 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 124 | /* DDR Setup */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 125 | #define CONFIG_VERY_BIG_RAM |
Wolfgang Denk | dc25d15 | 2010-10-04 19:58:00 +0200 | [diff] [blame] | 126 | #ifdef CONFIG_DDR2 |
york | cc1415c | 2010-07-02 22:25:58 +0000 | [diff] [blame] | 127 | #define CONFIG_FSL_DDR2 |
| 128 | #else |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 129 | #define CONFIG_FSL_DDR3 1 |
york | cc1415c | 2010-07-02 22:25:58 +0000 | [diff] [blame] | 130 | #endif |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 131 | |
Wolfgang Denk | 1d695be | 2009-07-07 22:35:02 +0200 | [diff] [blame] | 132 | /* ECC will be enabled based on perf_mode environment variable */ |
| 133 | /* #define CONFIG_DDR_ECC */ |
| 134 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 135 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 136 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 137 | |
| 138 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 139 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 140 | |
| 141 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 142 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 143 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 144 | |
| 145 | /* I2C addresses of SPD EEPROMs */ |
york | cc1415c | 2010-07-02 22:25:58 +0000 | [diff] [blame] | 146 | #define CONFIG_DDR_SPD |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 147 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ |
Kumar Gala | c68e86c | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 148 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 149 | |
| 150 | /* These are used when DDR doesn't use SPD. */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 151 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ |
| 152 | |
| 153 | /* Default settings for "stable" mode */ |
| 154 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
| 155 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 |
| 156 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
| 157 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 |
| 158 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
| 159 | #define CONFIG_SYS_DDR_TIMING_0 0x00330804 |
| 160 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 |
| 161 | #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 |
| 162 | #define CONFIG_SYS_DDR_MODE_1 0x00421422 |
| 163 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| 164 | #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 |
| 165 | #define CONFIG_SYS_DDR_INTERVAL 0x61800100 |
| 166 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 167 | #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 |
| 168 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
| 169 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 |
| 170 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 |
| 171 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 |
| 172 | #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ |
| 173 | #define CONFIG_SYS_DDR_CONTROL2 0x24400011 |
| 174 | #define CONFIG_SYS_DDR_CDR1 0x00040000 |
| 175 | #define CONFIG_SYS_DDR_CDR2 0x00000000 |
| 176 | |
| 177 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
| 178 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
| 179 | #define CONFIG_SYS_DDR_SBE 0x00010000 |
| 180 | |
| 181 | /* Settings that differ for "performance" mode */ |
| 182 | #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ |
| 183 | #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ |
| 184 | #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 |
| 185 | #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 |
| 186 | #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce |
| 187 | #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ |
| 188 | |
| 189 | /* |
| 190 | * The following set of values were tested for DDR2 |
| 191 | * with a DDR3 to DDR2 interposer |
| 192 | * |
| 193 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 194 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
| 195 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 |
| 196 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 |
| 197 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 |
| 198 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| 199 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 |
| 200 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 201 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 |
| 202 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
| 203 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| 204 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 |
| 205 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
| 206 | * |
| 207 | */ |
| 208 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 209 | /* |
| 210 | * Memory map |
| 211 | * |
| 212 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| 213 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| 214 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable |
| 215 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable |
| 216 | * |
| 217 | * Localbus cacheable (TBD) |
| 218 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
| 219 | * |
| 220 | * Localbus non-cacheable |
| 221 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable |
| 222 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
| 223 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
| 224 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 225 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| 226 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| 227 | */ |
| 228 | |
| 229 | /* |
| 230 | * Local Bus Definitions |
| 231 | */ |
| 232 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
| 233 | #ifdef CONFIG_PHYS_64BIT |
| 234 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
| 235 | #else |
| 236 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 237 | #endif |
| 238 | |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 239 | #define CONFIG_FLASH_BR_PRELIM \ |
| 240 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 241 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
| 242 | |
| 243 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| 244 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
| 245 | |
| 246 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
| 247 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 248 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 249 | |
| 250 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 251 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 252 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 253 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 254 | |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 255 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 256 | |
| 257 | #define CONFIG_FLASH_CFI_DRIVER |
| 258 | #define CONFIG_SYS_FLASH_CFI |
| 259 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 260 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 |
| 261 | |
| 262 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
| 263 | |
york | cc1415c | 2010-07-02 22:25:58 +0000 | [diff] [blame] | 264 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
Timur Tabi | 4f332d2 | 2010-04-01 10:49:42 -0500 | [diff] [blame] | 265 | #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ |
| 266 | |
| 267 | #ifdef CONFIG_FSL_NGPIXIS |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 268 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
| 269 | #ifdef CONFIG_PHYS_64BIT |
| 270 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
| 271 | #else |
| 272 | #define PIXIS_BASE_PHYS PIXIS_BASE |
| 273 | #endif |
| 274 | |
| 275 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| 276 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
| 277 | |
Timur Tabi | 4f332d2 | 2010-04-01 10:49:42 -0500 | [diff] [blame] | 278 | #define PIXIS_LBMAP_SWITCH 7 |
| 279 | #define PIXIS_LBMAP_MASK 0xf0 |
| 280 | #define PIXIS_LBMAP_SHIFT 4 |
| 281 | #define PIXIS_LBMAP_ALTBANK 0x20 |
| 282 | #endif |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 283 | |
| 284 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 285 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
york | 046d78d | 2010-07-02 22:26:03 +0000 | [diff] [blame] | 286 | #ifdef CONFIG_PHYS_64BIT |
| 287 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
| 288 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR |
| 289 | /* The assembler doesn't like typecast */ |
| 290 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
| 291 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ |
| 292 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
| 293 | #else |
| 294 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ |
| 295 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 |
| 296 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS |
| 297 | #endif |
Wolfgang Denk | 1c2e98e | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 298 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 299 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 300 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 301 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 302 | |
| 303 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 304 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
| 305 | |
| 306 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| 307 | #ifdef CONFIG_PHYS_64BIT |
| 308 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull |
| 309 | #else |
| 310 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 311 | #endif |
| 312 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 313 | CONFIG_SYS_NAND_BASE + 0x40000, \ |
| 314 | CONFIG_SYS_NAND_BASE + 0x80000,\ |
| 315 | CONFIG_SYS_NAND_BASE + 0xC0000} |
| 316 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 |
| 317 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 318 | #define CONFIG_CMD_NAND 1 |
| 319 | #define CONFIG_NAND_FSL_ELBC 1 |
| 320 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 321 | |
| 322 | /* NAND flash config */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 323 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 324 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 325 | | BR_PS_8 /* Port Size = 8bit */ \ |
| 326 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 327 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 328 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 329 | | OR_FCM_PGS /* Large Page*/ \ |
| 330 | | OR_FCM_CSCT \ |
| 331 | | OR_FCM_CST \ |
| 332 | | OR_FCM_CHT \ |
| 333 | | OR_FCM_SCY_1 \ |
| 334 | | OR_FCM_TRLX \ |
| 335 | | OR_FCM_EHTR) |
| 336 | |
| 337 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 338 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 339 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
| 340 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 341 | |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 342 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 343 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 344 | | BR_PS_8 /* Port Size = 8bit */ \ |
| 345 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 346 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 347 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 348 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 349 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 350 | | BR_PS_8 /* Port Size = 8bit */ \ |
| 351 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 352 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 353 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 354 | |
Timur Tabi | b56570c | 2012-07-06 07:39:26 +0000 | [diff] [blame] | 355 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 356 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 357 | | BR_PS_8 /* Port Size = 8bit */ \ |
| 358 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 359 | | BR_V) /* valid */ |
Matthew McClintock | 48aab14 | 2011-04-05 14:39:33 -0500 | [diff] [blame] | 360 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 361 | |
| 362 | /* Serial Port - controlled on board with jumper J8 |
| 363 | * open - index 2 |
| 364 | * shorted - index 1 |
| 365 | */ |
| 366 | #define CONFIG_CONS_INDEX 1 |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 367 | #define CONFIG_SYS_NS16550 |
| 368 | #define CONFIG_SYS_NS16550_SERIAL |
| 369 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 370 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| 371 | |
| 372 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Timur Tabi | 9bde036 | 2012-05-04 12:21:27 +0000 | [diff] [blame] | 373 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 374 | |
| 375 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 376 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| 377 | |
| 378 | /* Use the HUSH parser */ |
| 379 | #define CONFIG_SYS_HUSH_PARSER |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 380 | |
| 381 | /* |
| 382 | * Pass open firmware flat tree |
| 383 | */ |
| 384 | #define CONFIG_OF_LIBFDT 1 |
| 385 | #define CONFIG_OF_BOARD_SETUP 1 |
| 386 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| 387 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 388 | /* I2C */ |
| 389 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 390 | #define CONFIG_HARD_I2C /* I2C with hardware support */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 391 | #define CONFIG_I2C_MULTI_BUS |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 392 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 393 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 394 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 395 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ |
| 396 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
| 397 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 |
| 398 | |
| 399 | /* |
| 400 | * I2C2 EEPROM |
| 401 | */ |
| 402 | #define CONFIG_ID_EEPROM |
| 403 | #ifdef CONFIG_ID_EEPROM |
| 404 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 405 | #endif |
| 406 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 407 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 408 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 409 | |
| 410 | /* |
Jerry Huang | 6326092 | 2011-01-24 17:09:56 +0000 | [diff] [blame] | 411 | * eSPI - Enhanced SPI |
| 412 | */ |
| 413 | #define CONFIG_FSL_ESPI |
| 414 | |
| 415 | #define CONFIG_SPI_FLASH |
| 416 | #define CONFIG_SPI_FLASH_SPANSION |
| 417 | |
| 418 | #define CONFIG_CMD_SF |
| 419 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
| 420 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
| 421 | |
| 422 | /* |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 423 | * General PCI |
| 424 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 425 | */ |
| 426 | |
| 427 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ |
Kumar Gala | 9d4d751 | 2010-12-17 07:01:00 -0600 | [diff] [blame] | 428 | #define CONFIG_SYS_PCIE3_NAME "Slot 1" |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 429 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
| 430 | #ifdef CONFIG_PHYS_64BIT |
Kumar Gala | e1cb3db | 2009-06-18 08:39:42 -0500 | [diff] [blame] | 431 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 432 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
| 433 | #else |
| 434 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
| 435 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
| 436 | #endif |
| 437 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| 438 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
| 439 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 440 | #ifdef CONFIG_PHYS_64BIT |
| 441 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
| 442 | #else |
| 443 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
| 444 | #endif |
| 445 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 446 | |
| 447 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ |
Kumar Gala | 9d4d751 | 2010-12-17 07:01:00 -0600 | [diff] [blame] | 448 | #define CONFIG_SYS_PCIE2_NAME "ULI" |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 449 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 450 | #ifdef CONFIG_PHYS_64BIT |
Kumar Gala | e1cb3db | 2009-06-18 08:39:42 -0500 | [diff] [blame] | 451 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 452 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 453 | #else |
| 454 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| 455 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| 456 | #endif |
| 457 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| 458 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| 459 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 460 | #ifdef CONFIG_PHYS_64BIT |
| 461 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
| 462 | #else |
| 463 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| 464 | #endif |
| 465 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 466 | |
| 467 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ |
Kumar Gala | 9d4d751 | 2010-12-17 07:01:00 -0600 | [diff] [blame] | 468 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 469 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
| 470 | #ifdef CONFIG_PHYS_64BIT |
Kumar Gala | e1cb3db | 2009-06-18 08:39:42 -0500 | [diff] [blame] | 471 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 472 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
| 473 | #else |
| 474 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
| 475 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
| 476 | #endif |
| 477 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 478 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
| 479 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 480 | #ifdef CONFIG_PHYS_64BIT |
| 481 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
| 482 | #else |
| 483 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
| 484 | #endif |
| 485 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 486 | |
| 487 | #if defined(CONFIG_PCI) |
| 488 | |
| 489 | /*PCIE video card used*/ |
| 490 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
| 491 | |
| 492 | /* video */ |
| 493 | #define CONFIG_VIDEO |
| 494 | |
| 495 | #if defined(CONFIG_VIDEO) |
| 496 | #define CONFIG_BIOSEMU |
| 497 | #define CONFIG_CFB_CONSOLE |
| 498 | #define CONFIG_VIDEO_SW_CURSOR |
| 499 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| 500 | #define CONFIG_ATI_RADEON_FB |
| 501 | #define CONFIG_VIDEO_LOGO |
| 502 | /*#define CONFIG_CONSOLE_CURSOR*/ |
| 503 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| 504 | #endif |
Li Yang | 1f558db | 2010-12-30 11:17:44 -0600 | [diff] [blame] | 505 | |
| 506 | /* SRIO1 uses the same window as PCIE2 mem window */ |
| 507 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 |
| 508 | #ifdef CONFIG_PHYS_64BIT |
| 509 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull |
| 510 | #else |
| 511 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 |
| 512 | #endif |
| 513 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ |
| 514 | |
| 515 | /* SRIO2 uses the same window as PCIE1 mem window */ |
| 516 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000 |
| 517 | #ifdef CONFIG_PHYS_64BIT |
| 518 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull |
| 519 | #else |
| 520 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000 |
| 521 | #endif |
| 522 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 523 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 524 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 525 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 526 | #define CONFIG_DOS_PARTITION |
| 527 | #define CONFIG_SCSI_AHCI |
| 528 | |
| 529 | #ifdef CONFIG_SCSI_AHCI |
| 530 | #define CONFIG_SATA_ULI5288 |
| 531 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 532 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 533 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) |
| 534 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE |
| 535 | #endif /* SCSI */ |
| 536 | |
| 537 | #endif /* CONFIG_PCI */ |
| 538 | |
| 539 | |
| 540 | #if defined(CONFIG_TSEC_ENET) |
| 541 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 542 | #define CONFIG_MII 1 /* MII PHY management */ |
| 543 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 544 | #define CONFIG_TSEC1 1 |
| 545 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 546 | #define CONFIG_TSEC2 1 |
| 547 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 548 | #define CONFIG_TSEC3 1 |
| 549 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 550 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 551 | #define CONFIG_FSL_SGMII_RISER 1 |
| 552 | #define SGMII_RISER_PHY_OFFSET 0x1b |
| 553 | |
| 554 | #ifdef CONFIG_FSL_SGMII_RISER |
| 555 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ |
| 556 | #endif |
| 557 | |
| 558 | #define TSEC1_PHY_ADDR 0 |
| 559 | #define TSEC2_PHY_ADDR 1 |
| 560 | #define TSEC3_PHY_ADDR 2 |
| 561 | |
| 562 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 563 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 564 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 565 | |
| 566 | #define TSEC1_PHYIDX 0 |
| 567 | #define TSEC2_PHYIDX 0 |
| 568 | #define TSEC3_PHYIDX 0 |
| 569 | |
| 570 | #define CONFIG_ETHPRIME "eTSEC1" |
| 571 | |
| 572 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 573 | #endif /* CONFIG_TSEC_ENET */ |
| 574 | |
| 575 | /* |
| 576 | * Environment |
| 577 | */ |
Jerry Huang | 2c766ba | 2011-01-24 17:09:54 +0000 | [diff] [blame] | 578 | #if defined(CONFIG_SDCARD) |
| 579 | #define CONFIG_ENV_IS_IN_MMC |
Fabio Estevam | ae8c45e | 2012-01-11 09:20:50 +0000 | [diff] [blame] | 580 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
Jerry Huang | 2c766ba | 2011-01-24 17:09:54 +0000 | [diff] [blame] | 581 | #define CONFIG_ENV_SIZE 0x2000 |
| 582 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
Jerry Huang | 6326092 | 2011-01-24 17:09:56 +0000 | [diff] [blame] | 583 | #elif defined(CONFIG_SPIFLASH) |
| 584 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 585 | #define CONFIG_ENV_SPI_BUS 0 |
| 586 | #define CONFIG_ENV_SPI_CS 0 |
| 587 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 |
| 588 | #define CONFIG_ENV_SPI_MODE 0 |
| 589 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
| 590 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
| 591 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
Jerry Huang | 2c766ba | 2011-01-24 17:09:54 +0000 | [diff] [blame] | 592 | #else |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 593 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 594 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
| 595 | #define CONFIG_ENV_ADDR 0xfff80000 |
| 596 | #else |
| 597 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 598 | #endif |
| 599 | #define CONFIG_ENV_SIZE 0x2000 |
| 600 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
Jerry Huang | 2c766ba | 2011-01-24 17:09:54 +0000 | [diff] [blame] | 601 | #endif |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 602 | |
| 603 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 604 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 605 | |
| 606 | /* |
| 607 | * Command line configuration. |
| 608 | */ |
| 609 | #include <config_cmd_default.h> |
| 610 | |
| 611 | #define CONFIG_CMD_IRQ |
| 612 | #define CONFIG_CMD_PING |
| 613 | #define CONFIG_CMD_I2C |
| 614 | #define CONFIG_CMD_MII |
| 615 | #define CONFIG_CMD_ELF |
| 616 | #define CONFIG_CMD_IRQ |
| 617 | #define CONFIG_CMD_SETEXPR |
Becky Bruce | ee888da | 2010-06-17 11:37:25 -0500 | [diff] [blame] | 618 | #define CONFIG_CMD_REGINFO |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 619 | |
| 620 | #if defined(CONFIG_PCI) |
| 621 | #define CONFIG_CMD_PCI |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 622 | #define CONFIG_CMD_NET |
| 623 | #define CONFIG_CMD_SCSI |
| 624 | #define CONFIG_CMD_EXT2 |
| 625 | #endif |
| 626 | |
Roy Zang | 0770d30 | 2009-09-10 14:44:48 +0800 | [diff] [blame] | 627 | /* |
| 628 | * USB |
| 629 | */ |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 630 | #define CONFIG_HAS_FSL_DR_USB |
| 631 | #ifdef CONFIG_HAS_FSL_DR_USB |
Jerry Huang | b0bd775 | 2011-01-24 17:09:53 +0000 | [diff] [blame] | 632 | #define CONFIG_USB_EHCI |
| 633 | |
| 634 | #ifdef CONFIG_USB_EHCI |
Roy Zang | 0770d30 | 2009-09-10 14:44:48 +0800 | [diff] [blame] | 635 | #define CONFIG_CMD_USB |
| 636 | #define CONFIG_USB_STORAGE |
Roy Zang | 0770d30 | 2009-09-10 14:44:48 +0800 | [diff] [blame] | 637 | #define CONFIG_USB_EHCI_FSL |
| 638 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
Jerry Huang | b0bd775 | 2011-01-24 17:09:53 +0000 | [diff] [blame] | 639 | #endif |
ramneek mehresh | 3d33963 | 2012-04-18 19:39:53 +0000 | [diff] [blame] | 640 | #endif |
Roy Zang | 0770d30 | 2009-09-10 14:44:48 +0800 | [diff] [blame] | 641 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 642 | /* |
Jerry Huang | b0bd775 | 2011-01-24 17:09:53 +0000 | [diff] [blame] | 643 | * SDHC/MMC |
| 644 | */ |
| 645 | #define CONFIG_MMC |
| 646 | |
| 647 | #ifdef CONFIG_MMC |
| 648 | #define CONFIG_FSL_ESDHC |
| 649 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
| 650 | #define CONFIG_CMD_MMC |
| 651 | #define CONFIG_GENERIC_MMC |
| 652 | #endif |
| 653 | |
| 654 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) |
| 655 | #define CONFIG_CMD_EXT2 |
| 656 | #define CONFIG_CMD_FAT |
| 657 | #define CONFIG_DOS_PARTITION |
| 658 | #endif |
| 659 | |
| 660 | /* |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 661 | * Miscellaneous configurable options |
| 662 | */ |
| 663 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Kim Phillips | f7758c1 | 2010-07-14 19:47:18 -0500 | [diff] [blame] | 664 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 665 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 666 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 667 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
| 668 | #if defined(CONFIG_CMD_KGDB) |
| 669 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 670 | #else |
| 671 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 672 | #endif |
| 673 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 674 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 675 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 676 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 677 | |
| 678 | /* |
| 679 | * For booting Linux, the board info and command line data |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 680 | * have to be in the first 64 MB of memory, since this is |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 681 | * the maximum mapped by the Linux kernel during initialization. |
| 682 | */ |
Kumar Gala | 39ffcc1 | 2011-04-28 10:13:41 -0500 | [diff] [blame] | 683 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
| 684 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 685 | |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 686 | #if defined(CONFIG_CMD_KGDB) |
| 687 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 688 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 689 | #endif |
| 690 | |
| 691 | /* |
| 692 | * Environment Configuration |
| 693 | */ |
| 694 | |
| 695 | /* The mac addresses for all ethernet interface */ |
| 696 | #if defined(CONFIG_TSEC_ENET) |
| 697 | #define CONFIG_HAS_ETH0 |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 698 | #define CONFIG_HAS_ETH1 |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 699 | #define CONFIG_HAS_ETH2 |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 700 | #endif |
| 701 | |
| 702 | #define CONFIG_IPADDR 192.168.1.254 |
| 703 | |
| 704 | #define CONFIG_HOSTNAME unknown |
Joe Hershberger | 257ff78 | 2011-10-13 13:03:47 +0000 | [diff] [blame] | 705 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
Joe Hershberger | e4da248 | 2011-10-13 13:03:48 +0000 | [diff] [blame] | 706 | #define CONFIG_BOOTFILE "uImage" |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 707 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 708 | |
| 709 | #define CONFIG_SERVERIP 192.168.1.1 |
| 710 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 711 | #define CONFIG_NETMASK 255.255.255.0 |
| 712 | |
| 713 | /* default location for tftp and bootm */ |
| 714 | #define CONFIG_LOADADDR 1000000 |
| 715 | |
| 716 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 717 | |
| 718 | #define CONFIG_BAUDRATE 115200 |
| 719 | |
| 720 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Li Yang | 9c30e03 | 2011-01-24 17:09:52 +0000 | [diff] [blame] | 721 | "perf_mode=performance\0" \ |
Ramneek Mehresh | a0cce27 | 2011-06-07 10:10:43 +0000 | [diff] [blame] | 722 | "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ |
| 723 | "usb1:dr_mode=host,phy_type=ulpi\0" \ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 724 | "netdev=eth0\0" \ |
| 725 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ |
| 726 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 727 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 728 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 729 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ |
| 730 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 731 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ |
Li Yang | 9c30e03 | 2011-01-24 17:09:52 +0000 | [diff] [blame] | 732 | "satabootcmd=setenv bootargs root=/dev/$bdev rw " \ |
| 733 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 734 | "tftp $loadaddr $bootfile;" \ |
| 735 | "tftp $fdtaddr $fdtfile;" \ |
| 736 | "bootm $loadaddr - $fdtaddr" \ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 737 | "consoledev=ttyS0\0" \ |
| 738 | "ramdiskaddr=2000000\0" \ |
| 739 | "ramdiskfile=p2020ds/ramdisk.uboot\0" \ |
| 740 | "fdtaddr=c00000\0" \ |
Li Yang | 9c30e03 | 2011-01-24 17:09:52 +0000 | [diff] [blame] | 741 | "othbootargs=cache-sram-size=0x10000\0" \ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 742 | "fdtfile=p2020ds/p2020ds.dtb\0" \ |
Li Yang | 9c30e03 | 2011-01-24 17:09:52 +0000 | [diff] [blame] | 743 | "bdev=sda3\0" \ |
| 744 | "partition=scsi 0:0\0" |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 745 | |
| 746 | #define CONFIG_HDBOOT \ |
| 747 | "setenv bootargs root=/dev/$bdev rw " \ |
| 748 | "console=$consoledev,$baudrate $othbootargs;" \ |
Li Yang | 9c30e03 | 2011-01-24 17:09:52 +0000 | [diff] [blame] | 749 | "ext2load $partition $loadaddr $bootfile;" \ |
| 750 | "ext2load $partition $fdtaddr $fdtfile;" \ |
Srikanth Srinivasan | 949a2d5 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 751 | "bootm $loadaddr - $fdtaddr" |
| 752 | |
| 753 | #define CONFIG_NFSBOOTCOMMAND \ |
| 754 | "setenv bootargs root=/dev/nfs rw " \ |
| 755 | "nfsroot=$serverip:$rootpath " \ |
| 756 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 757 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 758 | "tftp $loadaddr $bootfile;" \ |
| 759 | "tftp $fdtaddr $fdtfile;" \ |
| 760 | "bootm $loadaddr - $fdtaddr" |
| 761 | |
| 762 | #define CONFIG_RAMBOOTCOMMAND \ |
| 763 | "setenv bootargs root=/dev/ram rw " \ |
| 764 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 765 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 766 | "tftp $loadaddr $bootfile;" \ |
| 767 | "tftp $fdtaddr $fdtfile;" \ |
| 768 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 769 | |
| 770 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT |
| 771 | |
| 772 | #endif /* __CONFIG_H */ |