Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Carlo Caione | 72ad903 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 2 | /* |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 3 | * Configuration for Amlogic Meson 64bits SoCs |
Carlo Caione | 72ad903 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 4 | * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
Carlo Caione | 72ad903 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 7 | #ifndef __MESON64_CONFIG_H |
| 8 | #define __MESON64_CONFIG_H |
| 9 | |
| 10 | /* Generic Interrupt Controller Definitions */ |
Neil Armstrong | 0fca923 | 2018-09-05 15:56:12 +0200 | [diff] [blame] | 11 | #if defined(CONFIG_MESON_AXG) |
| 12 | #define GICD_BASE 0xffc01000 |
| 13 | #define GICC_BASE 0xffc02000 |
| 14 | #else /* MESON GXL and GXBB */ |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 15 | #define GICD_BASE 0xc4301000 |
| 16 | #define GICC_BASE 0xc4302000 |
Neil Armstrong | 0fca923 | 2018-09-05 15:56:12 +0200 | [diff] [blame] | 17 | #endif |
Carlo Caione | 72ad903 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 18 | |
| 19 | #define CONFIG_CPU_ARMV8 |
| 20 | #define CONFIG_REMAKE_ELF |
Carlo Caione | 72ad903 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 21 | #define CONFIG_ENV_SIZE 0x2000 |
| 22 | #define CONFIG_SYS_MAXARGS 32 |
| 23 | #define CONFIG_SYS_MALLOC_LEN (32 << 20) |
| 24 | #define CONFIG_SYS_CBSIZE 1024 |
Carlo Caione | 72ad903 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 25 | |
| 26 | #define CONFIG_SYS_SDRAM_BASE 0 |
Carlo Caione | 72ad903 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 27 | #define CONFIG_SYS_INIT_SP_ADDR 0x20000000 |
| 28 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 29 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ |
Carlo Caione | 72ad903 | 2016-06-10 20:18:22 +0200 | [diff] [blame] | 30 | |
Neil Armstrong | 2fbfcbb | 2018-07-27 14:10:00 +0200 | [diff] [blame] | 31 | /* ROM USB boot support, auto-execute boot.scr at scriptaddr */ |
| 32 | #define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ |
| 33 | "bootcmd_romusb=" \ |
| 34 | "if test \"${boot_source}\" = \"usb\" && " \ |
| 35 | "test -n \"${scriptaddr}\"; then " \ |
| 36 | "echo '(ROM USB boot)'; " \ |
| 37 | "source ${scriptaddr}; " \ |
| 38 | "fi\0" |
| 39 | |
| 40 | #define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance) \ |
| 41 | "romusb " |
| 42 | |
Neil Armstrong | 42fe74e | 2018-06-14 13:43:38 +0200 | [diff] [blame] | 43 | #ifdef CONFIG_CMD_USB |
| 44 | #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) |
| 45 | #else |
| 46 | #define BOOT_TARGET_DEVICES_USB(func) |
| 47 | #endif |
| 48 | |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 49 | #ifndef BOOT_TARGET_DEVICES |
Andreas Färber | d129668 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 50 | #define BOOT_TARGET_DEVICES(func) \ |
Neil Armstrong | 2fbfcbb | 2018-07-27 14:10:00 +0200 | [diff] [blame] | 51 | func(ROMUSB, romusb, na) \ |
xypron.glpk@gmx.de | 787b5d1 | 2017-04-15 21:30:39 +0200 | [diff] [blame] | 52 | func(MMC, mmc, 0) \ |
| 53 | func(MMC, mmc, 1) \ |
| 54 | func(MMC, mmc, 2) \ |
Neil Armstrong | 42fe74e | 2018-06-14 13:43:38 +0200 | [diff] [blame] | 55 | BOOT_TARGET_DEVICES_USB(func) \ |
Vagrant Cascadian | 69d4b99 | 2017-05-05 14:11:26 -0700 | [diff] [blame] | 56 | func(PXE, pxe, na) \ |
Andreas Färber | d129668 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 57 | func(DHCP, dhcp, na) |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 58 | #endif |
Andreas Färber | d129668 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 59 | |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 60 | #ifndef CONFIG_EXTRA_ENV_SETTINGS |
Andreas Färber | d129668 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 61 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Jerome Brunet | 7c3ca35 | 2018-10-24 16:27:51 +0200 | [diff] [blame] | 62 | "fdt_addr_r=0x08008000\0" \ |
| 63 | "scriptaddr=0x08000000\0" \ |
| 64 | "kernel_addr_r=0x08080000\0" \ |
Andreas Färber | d129668 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 65 | "pxefile_addr_r=0x01080000\0" \ |
xypron.glpk@gmx.de | 840e0af | 2017-04-14 20:04:46 +0200 | [diff] [blame] | 66 | "ramdisk_addr_r=0x13000000\0" \ |
Jerome Brunet | ff5ce03 | 2018-10-19 12:00:51 +0200 | [diff] [blame] | 67 | "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ |
Andreas Färber | d129668 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 68 | BOOTENV |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 69 | #endif |
Andreas Färber | d129668 | 2017-01-15 20:22:30 +0100 | [diff] [blame] | 70 | |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 71 | #include <config_distro_bootcmd.h> |
xypron.glpk@gmx.de | 07fee66 | 2017-04-14 19:54:40 +0200 | [diff] [blame] | 72 | |
Jerome Brunet | 32bacc5 | 2018-10-25 16:41:37 +0200 | [diff] [blame] | 73 | #endif /* __MESON64_CONFIG_H */ |