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git01.mediatek.com / filogic / uboot / 0f97ed01b6c28cd892b948608a098ba63b5eb4ed / . / arch / arm / dts / imx8mq-pico-pi.dts
blob: d2af18ad0e13be800f25dd9bb6136b496fd779fd [file] [log] [blame]
Marek Vasut0f97ed02020-04-29 20:09:08 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2018 Wandboard, Org.
4 * Copyright 2017 NXP
5 *
6 * Author: Richard Hu <hakahu@gmail.com>
7 */
8
9/dts-v1/;
10
11#include "imx8mq.dtsi"
12
13/ {
14 model = "TechNexion PICO-PI-8M";
15 compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
16
17 chosen {
18 stdout-path = &uart1;
19 };
20
21 pmic_osc: clock-pmic {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <32768>;
25 clock-output-names = "pmic_osc";
26 };
27
28 reg_usb_otg_vbus: regulator-usb-otg-vbus {
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_otg_vbus>;
31 compatible = "regulator-fixed";
32 regulator-name = "usb_otg_vbus";
33 regulator-min-microvolt = <5000000>;
34 regulator-max-microvolt = <5000000>;
35 gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
36 };
37
38 reg_eth_phy: eth_phy {
39 compatible = "regulator-fixed";
40 regulator-name = "eth_phy_pwr";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
44 };
45};
46
47&fec1 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_fec1>;
50 phy-mode = "rgmii-id";
51 phy-handle = <&ethphy0>;
52 phy-supply = <&reg_eth_phy>;
53 phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
54 phy-reset-duration = <100>;
55 phy-reset-post-delay = <100>;
56 fsl,magic-packet;
57 status = "okay";
58
59 mdio {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 ethphy0: ethernet-phy@1 {
64 compatible = "ethernet-phy-ieee802.3-c22";
65 reg = <1>;
66 };
67 };
68};
69
70&i2c1 {
71 clock-frequency = <100000>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_i2c1>;
74 status = "okay";
75
76 pmic: pmic@4b {
77 reg = <0x4b>;
78 compatible = "rohm,bd71837";
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_pmic>;
81 clocks = <&pmic_osc>;
82 clock-names = "osc";
83 clock-output-names = "pmic_clk";
84 interrupt-parent = <&gpio1>;
85 interrupts = <3 GPIO_ACTIVE_LOW>;
86 interrupt-names = "irq";
87
88 regulators {
89 buck1: BUCK1 {
90 regulator-name = "buck1";
91 regulator-min-microvolt = <700000>;
92 regulator-max-microvolt = <1300000>;
93 regulator-boot-on;
94 regulator-ramp-delay = <1250>;
95 rohm,dvs-run-voltage = <900000>;
96 rohm,dvs-idle-voltage = <850000>;
97 rohm,dvs-suspend-voltage = <800000>;
98 };
99
100 buck2: BUCK2 {
101 regulator-name = "buck2";
102 regulator-min-microvolt = <700000>;
103 regulator-max-microvolt = <1300000>;
104 regulator-boot-on;
105 regulator-ramp-delay = <1250>;
106 rohm,dvs-run-voltage = <1000000>;
107 rohm,dvs-idle-voltage = <900000>;
108 };
109
110 buck3: BUCK3 {
111 regulator-name = "buck3";
112 regulator-min-microvolt = <700000>;
113 regulator-max-microvolt = <1300000>;
114 regulator-boot-on;
115 rohm,dvs-run-voltage = <1000000>;
116 };
117
118 buck4: BUCK4 {
119 regulator-name = "buck4";
120 regulator-min-microvolt = <700000>;
121 regulator-max-microvolt = <1300000>;
122 regulator-boot-on;
123 rohm,dvs-run-voltage = <1000000>;
124 };
125
126 buck5: BUCK5 {
127 regulator-name = "buck5";
128 regulator-min-microvolt = <700000>;
129 regulator-max-microvolt = <1350000>;
130 regulator-boot-on;
131 };
132
133 buck6: BUCK6 {
134 regulator-name = "buck6";
135 regulator-min-microvolt = <3000000>;
136 regulator-max-microvolt = <3300000>;
137 regulator-boot-on;
138 };
139
140 buck7: BUCK7 {
141 regulator-name = "buck7";
142 regulator-min-microvolt = <1605000>;
143 regulator-max-microvolt = <1995000>;
144 regulator-boot-on;
145 };
146
147 buck8: BUCK8 {
148 regulator-name = "buck8";
149 regulator-min-microvolt = <800000>;
150 regulator-max-microvolt = <1400000>;
151 regulator-boot-on;
152 };
153
154 ldo1: LDO1 {
155 regulator-name = "ldo1";
156 regulator-min-microvolt = <3000000>;
157 regulator-max-microvolt = <3300000>;
158 regulator-boot-on;
159 regulator-always-on;
160 };
161
162 ldo2: LDO2 {
163 regulator-name = "ldo2";
164 regulator-min-microvolt = <900000>;
165 regulator-max-microvolt = <900000>;
166 regulator-boot-on;
167 regulator-always-on;
168 };
169
170 ldo3: LDO3 {
171 regulator-name = "ldo3";
172 regulator-min-microvolt = <1800000>;
173 regulator-max-microvolt = <3300000>;
174 regulator-boot-on;
175 };
176
177 ldo4: LDO4 {
178 regulator-name = "ldo4";
179 regulator-min-microvolt = <900000>;
180 regulator-max-microvolt = <1800000>;
181 regulator-boot-on;
182 };
183
184 ldo5: LDO5 {
185 regulator-name = "ldo5";
186 regulator-min-microvolt = <1800000>;
187 regulator-max-microvolt = <3300000>;
188 regulator-boot-on;
189 };
190
191 ldo6: LDO6 {
192 regulator-name = "ldo6";
193 regulator-min-microvolt = <900000>;
194 regulator-max-microvolt = <1800000>;
195 regulator-boot-on;
196 };
197
198 ldo7: LDO7 {
199 regulator-name = "ldo7";
200 regulator-min-microvolt = <1800000>;
201 regulator-max-microvolt = <3300000>;
202 regulator-boot-on;
203 };
204 };
205 };
206};
207
208&i2c2 {
209 clock-frequency = <100000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c2>;
212 status = "okay";
213};
214
215&uart1 { /* console */
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_uart1>;
218 status = "okay";
219};
220
221&usdhc1 {
222 pinctrl-names = "default", "state_100mhz", "state_200mhz";
223 pinctrl-0 = <&pinctrl_usdhc1>;
224 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
225 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
226 bus-width = <8>;
227 non-removable;
228 status = "okay";
229};
230
231&usdhc2 {
232 pinctrl-names = "default", "state_100mhz", "state_200mhz";
233 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
234 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
235 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
236 bus-width = <4>;
237 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
238 status = "okay";
239};
240
241&usb3_phy0 {
242 status = "okay";
243};
244
245&usb3_phy1 {
246 status = "okay";
247};
248
249&usb_dwc3_1 {
250 dr_mode = "host";
251 status = "okay";
252};
253
254&wdog1 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_wdog>;
257 fsl,ext-reset-output;
258 status = "okay";
259};
260
261&iomuxc {
262 pinctrl_fec1: fec1grp {
263 fsl,pins = <
264 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
265 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
266 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
267 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
268 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
269 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
270 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
271 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
272 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
273 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
274 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
275 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
276 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
277 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
278 MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
279 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
280 >;
281 };
282
283 pinctrl_i2c1: i2c1grp {
284 fsl,pins = <
285 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
286 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
287 >;
288 };
289
290 pinctrl_i2c2: i2c2grp {
291 fsl,pins = <
292 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
293 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
294 >;
295 };
296
297 pinctrl_otg_vbus: otgvbusgrp {
298 fsl,pins = <
299 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
300 >;
301 };
302
303 pinctrl_pmic: pmicirq {
304 fsl,pins = <
305 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
306 >;
307 };
308
309 pinctrl_uart1: uart1grp {
310 fsl,pins = <
311 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
312 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
313 >;
314 };
315
316 pinctrl_uart2: uart2grp {
317 fsl,pins = <
318 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
319 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
320 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
321 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
322 >;
323 };
324
325 pinctrl_usdhc1: usdhc1grp {
326 fsl,pins = <
327 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
328 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
329 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
330 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
331 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
332 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
333 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
334 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
335 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
336 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
337 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
338 >;
339 };
340
341 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
342 fsl,pins = <
343 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
344 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
345 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
346 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
347 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
348 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
349 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
350 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
351 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
352 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
353 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
354 >;
355 };
356
357 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
358 fsl,pins = <
359 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
360 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
361 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
362 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
363 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
364 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
365 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
366 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
367 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
368 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
369 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
370 >;
371 };
372
373 pinctrl_usdhc2_gpio: usdhc2grpgpio {
374 fsl,pins = <
375 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
376 >;
377 };
378
379 pinctrl_usdhc2: usdhc2grp {
380 fsl,pins = <
381 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
382 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
383 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
384 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
385 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
386 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
387 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
388 >;
389 };
390
391 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
392 fsl,pins = <
393 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
394 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
395 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
396 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
397 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
398 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
399 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
400 >;
401 };
402
403 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
404 fsl,pins = <
405 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
406 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
407 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
408 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
409 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
410 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
411 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
412 >;
413 };
414
415 pinctrl_wdog: wdoggrp {
416 fsl,pins = <
417 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
418 >;
419 };
420};