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git01.mediatek.com / filogic / uboot / 0f97ed01b6c28cd892b948608a098ba63b5eb4ed / . / arch / arm / dts / imx53-m53menlo.dts
blob: a6805eca9d08171c60d3b3a8b7b602cb1eaa4379 [file] [log] [blame]
Marek Vasutc1876802019-06-09 18:46:42 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2019 Marek Vasut <marex@denx.de>
4 */
5
6/dts-v1/;
7#include "imx53-m53.dtsi"
8#include "imx53-m53menlo-u-boot.dtsi"
9
10/ {
11 model = "MENLO M53 EMBEDDED DEVICE";
12 compatible = "menlo,m53menlo", "fsl,imx53";
13
14 leds {
15 compatible = "gpio-leds";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_led>;
18
19 user1 {
20 label = "TestLed601";
21 gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>;
22 linux,default-trigger = "mmc0";
23 };
24
25 user2 {
26 label = "TestLed602";
27 gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
28 linux,default-trigger = "heartbeat";
29 };
30
31 eth {
32 label = "EthLedYe";
33 gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
34 linux,default-trigger = "none";
35 };
36 };
37
38 panel {
39 compatible = "edt,etm070080dh6";
40 enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
41
42 port {
43 panel_in: endpoint {
44 remote-endpoint = <&lvds0_out>;
45 };
46 };
47 };
48
49 reg_usbh1_vbus: regulator-usbh1-vbus {
50 compatible = "regulator-fixed";
51 regulator-name = "vbus";
52 regulator-min-microvolt = <5000000>;
53 regulator-max-microvolt = <5000000>;
54 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
55 };
56};
57
58&can1 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_can1>;
61 status = "okay";
62};
63
64&can2 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_can2>;
67 status = "okay";
68};
69
70&clks {
71 assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>,
72 <&clks IMX5_CLK_CKO1_PODF>,
73 <&clks IMX5_CLK_CKO1>;
74 assigned-clock-parents = <&clks IMX5_CLK_AHB>;
75 assigned-clock-rates = <133333334>, <33333334>, <33333334>;
76};
77
78&esdhc1 {
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_esdhc1>;
81 cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
82 wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
83 status = "okay";
84};
85
86&fec {
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_fec>;
89 phy-mode = "rmii";
90 status = "okay";
91};
92
93&i2c1 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_i2c1>;
96 status = "okay";
97
98 touchscreen@38 {
99 compatible = "edt,edt-ft5x06";
100 reg = <0x38>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_edt_ft5x06>;
103 interrupt-parent = <&gpio6>;
104 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
105 reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
106 wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
107 };
108
109 eeprom@50 {
110 compatible = "atmel,24c64";
111 reg = <0x50>;
112 pagesize = <32>;
113 };
114
115 dac@60 {
116 compatible = "microchip,mcp4725";
117 reg = <0x60>;
118 };
119};
120
121&i2c2 {
122 touchscreen@41 {
123 status = "disabled";
124 };
125};
126
127&i2c3 {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_i2c3>;
130 status = "okay";
131};
132
133&iomuxc {
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_hog>;
136
137 imx53-m53evk {
138 hoggrp {
139 fsl,pins = <
140 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
141 MX53_PAD_EIM_EB3__GPIO2_31 0x1d5
142 MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5
143 MX53_PAD_GPIO_19__CCM_CLKO 0x1d5
144 MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5
145 MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5
146 MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5
147 MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5
148 MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5
149 MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5
150 MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5
151 MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5
152 MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5
153 MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5
154 >;
155 };
156
157 pinctrl_led: ledgrp {
158 fsl,pins = <
159 MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5
160 MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5
161 >;
162 };
163
164 pinctrl_can1: can1grp {
165 fsl,pins = <
166 MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4
167 MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4
168 >;
169 };
170
171 pinctrl_can2: can2grp {
172 fsl,pins = <
173 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4
174 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4
175 >;
176 };
177
178 pinctrl_display_gpio: display-gpiogrp {
179 fsl,pins = <
180 MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */
181 MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */
182 >;
183 };
184
185 pinctrl_edt_ft5x06: edt-ft5x06grp {
186 fsl,pins = <
187 MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */
188 MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */
189 MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */
190 >;
191 };
192
193 pinctrl_esdhc1: esdhc1grp {
194 fsl,pins = <
195 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
196 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
197 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
198 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
199 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
200 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
201 >;
202 };
203
204 pinctrl_fec: fecgrp {
205 fsl,pins = <
206 MX53_PAD_FEC_MDC__FEC_MDC 0x4
207 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
208 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
209 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
210 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
211 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
212 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
213 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
214 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
215 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
216 >;
217 };
218
219 pinctrl_i2c1: i2c1grp {
220 fsl,pins = <
221 MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4
222 MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4
223 >;
224 };
225
226 pinctrl_i2c3: i2c3grp {
227 fsl,pins = <
228 MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4
229 MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4
230 >;
231 };
232
233 pinctrl_lvds0: lvds0grp {
234 /* LVDS pins only have pin mux configuration */
235 fsl,pins = <
236 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
237 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
238 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
239 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
240 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
241 >;
242 };
243
244 pinctrl_uart1: uart1grp {
245 fsl,pins = <
246 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
247 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
248 >;
249 };
250
251 pinctrl_uart2: uart2grp {
252 fsl,pins = <
253 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
254 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
255 >;
256 };
257
258 pinctrl_usb: usbgrp {
259 fsl,pins = <
260 MX53_PAD_GPIO_2__GPIO1_2 0x1d5
261 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5
262 >;
263 };
264 };
265};
266
267&ldb {
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_lvds0>;
270 status = "okay";
271
272 lvds0: lvds-channel@0 {
273 reg = <0>;
274 fsl,data-mapping = "spwg";
275 fsl,data-width = <18>;
276 status = "okay";
277
278 port@2 {
279 reg = <2>;
280
281 lvds0_out: endpoint {
282 remote-endpoint = <&panel_in>;
283 };
284 };
285 };
286};
287
288&uart1 {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_uart1>;
291 status = "okay";
292};
293
294&uart2 {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_uart2>;
297 status = "okay";
298};
299
300&usbh1 {
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_usb>;
303 vbus-supply = <&reg_usbh1_vbus>;
304 phy_type = "utmi";
305 dr_mode = "peripheral";
306 status = "okay";
307};
308
309&usbotg {
310 dr_mode = "peripheral";
311 status = "okay";
312};