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git01.mediatek.com / filogic / uboot / 0f8c9768ff83244c49857a0c79fe04e947f387ce / . / include / configs / PM826.h
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wdenk0f8c9762002-08-19 11:57:05 +0000[diff] [blame^]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#undef CFG_RAMBOOT
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
39#define CONFIG_PM826 1 /* ...on a PM8260 module */
40
41#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
42
43#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
44
45#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
46
47#undef CONFIG_BOOTARGS
48#define CONFIG_BOOTCOMMAND \
49 "bootp; " \
50 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
51 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
52 "bootm"
53
54/* enable I2C and select the hardware/software driver */
55#undef CONFIG_HARD_I2C
56#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
57# define CFG_I2C_SPEED 50000
58# define CFG_I2C_SLAVE 0xFE
59/*
60 * Software (bit-bang) I2C driver configuration
61 */
62#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
63#define I2C_ACTIVE (iop->pdir |= 0x00010000)
64#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
65#define I2C_READ ((iop->pdat & 0x00010000) != 0)
66#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
67 else iop->pdat &= ~0x00010000
68#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
69 else iop->pdat &= ~0x00020000
70#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
71
72
73#define CONFIG_RTC_PCF8563
74#define CFG_I2C_RTC_ADDR 0x51
75
76/*
77 * select serial console configuration
78 *
79 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
80 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
81 * for SCC).
82 *
83 * if CONFIG_CONS_NONE is defined, then the serial console routines must
84 * defined elsewhere (for example, on the cogent platform, there are serial
85 * ports on the motherboard which are used for the serial console - see
86 * cogent/cma101/serial.[ch]).
87 */
88#define CONFIG_CONS_ON_SMC /* define if console on SMC */
89#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
90#undef CONFIG_CONS_NONE /* define if console on something else*/
91#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
92
93/*
94 * select ethernet configuration
95 *
96 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
97 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
98 * for FCC)
99 *
100 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
101 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
102 * from CONFIG_COMMANDS to remove support for networking.
103 */
104#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
105#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
106#undef CONFIG_ETHER_NONE /* define if ether on something else */
107#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
108
109#if (CONFIG_ETHER_INDEX == 1)
110/*
111 * - Rx-CLK is CLK11
112 * - Tx-CLK is CLK10
113 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
114 * - Enable Full Duplex in FSMR
115 */
116# define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
117# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
118# define CFG_CPMFCR_RAMTYPE 0
119# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
120
121#endif /* CONFIG_ETHER_INDEX */
122
123/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
124#define CONFIG_8260_CLKIN 64000000 /* in Hz */
125
126#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
127#define CONFIG_BAUDRATE 230400
128#else
129#define CONFIG_BAUDRATE 9600
130#endif
131
132#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
133#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
134
135#undef CONFIG_WATCHDOG /* watchdog disabled */
136
137#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
138
139#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
140 CFG_CMD_BEDBUG | \
141 CFG_CMD_DATE | \
142 CFG_CMD_EEPROM | \
143 CFG_CMD_DOC)
144
145/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
146#include <cmd_confdefs.h>
147
148/*
149 * Disk-On-Chip configuration
150 */
151
152#define CFG_DOC_SHORT_TIMEOUT
153#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
154
155#define CFG_DOC_SUPPORT_2000
156#define CFG_DOC_SUPPORT_MILLENNIUM
157
158/*
159 * Miscellaneous configurable options
160 */
161#define CFG_LONGHELP /* undef to save memory */
162#define CFG_PROMPT "=> " /* Monitor Command Prompt */
163#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
164#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
165#else
166#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
167#endif
168#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
169#define CFG_MAXARGS 16 /* max number of command args */
170#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
171
172#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
173#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
174
175#define CFG_LOAD_ADDR 0x100000 /* default load address */
176
177#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
178
179#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
180
181#define CFG_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
182
183/*
184 * For booting Linux, the board info and command line data
185 * have to be in the first 8 MB of memory, since this is
186 * the maximum mapped by the Linux kernel during initialization.
187 */
188#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
189
190/*-----------------------------------------------------------------------
191 * Flash and Boot ROM mapping
192 */
193
194#define CFG_BOOTROM_BASE 0x60000000
195#define CFG_BOOTROM_SIZE 0x00080000
196#define CFG_FLASH0_BASE 0x40000000
197#define CFG_FLASH0_SIZE 0x02000000
198#define CFG_DOC_BASE 0x60000000
199#define CFG_DOC_SIZE 0x00100000
200
201
202/* Flash bank size (for preliminary settings)
203 */
204#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
205
206/*-----------------------------------------------------------------------
207 * FLASH organization
208 */
209#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
210#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
211
212#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
213#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
214
215#if 0
216/* Start port with environment in flash; switch to EEPROM later */
217#define CFG_ENV_IS_IN_FLASH 1
218#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
219#define CFG_ENV_SIZE 0x40000
220#define CFG_ENV_SECT_SIZE 0x40000
221#else
222/* Final version: environment in EEPROM */
223#define CFG_ENV_IS_IN_EEPROM 1
224#define CFG_I2C_EEPROM_ADDR 0x58
225#define CFG_I2C_EEPROM_ADDR_LEN 1
226#define CFG_EEPROM_PAGE_WRITE_BITS 4
227#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
228#define CFG_ENV_OFFSET 0
229#define CFG_ENV_SIZE 2048
230#endif
231
232/*-----------------------------------------------------------------------
233 * Hard Reset Configuration Words
234 *
235 * if you change bits in the HRCW, you must also change the CFG_*
236 * defines for the various registers affected by the HRCW e.g. changing
237 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
238 */
239#if defined(CONFIG_BOOT_ROM)
240#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
241#else
242#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
243#endif
244
245/* no slaves so just fill with zeros */
246#define CFG_HRCW_SLAVE1 0
247#define CFG_HRCW_SLAVE2 0
248#define CFG_HRCW_SLAVE3 0
249#define CFG_HRCW_SLAVE4 0
250#define CFG_HRCW_SLAVE5 0
251#define CFG_HRCW_SLAVE6 0
252#define CFG_HRCW_SLAVE7 0
253
254/*-----------------------------------------------------------------------
255 * Internal Memory Mapped Register
256 */
257#define CFG_IMMR 0xF0000000
258
259/*-----------------------------------------------------------------------
260 * Definitions for initial stack pointer and data area (in DPRAM)
261 */
262#define CFG_INIT_RAM_ADDR CFG_IMMR
263#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
264#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
265#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
266#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
267
268/*-----------------------------------------------------------------------
269 * Start addresses for the final memory configuration
270 * (Set up by the startup code)
271 * Please note that CFG_SDRAM_BASE _must_ start at 0
272 *
273 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
274 * is mapped at SDRAM_BASE2_PRELIM.
275 */
276#define CFG_SDRAM_BASE 0x00000000
277#define CFG_FLASH_BASE CFG_FLASH0_BASE
278#define CFG_MONITOR_BASE TEXT_BASE
279#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
280#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
281
282#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
283# define CFG_RAMBOOT
284#endif
285
286/*
287 * Internal Definitions
288 *
289 * Boot Flags
290 */
291#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
292#define BOOTFLAG_WARM 0x02 /* Software reboot */
293
294
295/*-----------------------------------------------------------------------
296 * Cache Configuration
297 */
298#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
299#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
300# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
301#endif
302
303/*-----------------------------------------------------------------------
304 * HIDx - Hardware Implementation-dependent Registers 2-11
305 *-----------------------------------------------------------------------
306 * HID0 also contains cache control - initially enable both caches and
307 * invalidate contents, then the final state leaves only the instruction
308 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
309 * but Soft reset does not.
310 *
311 * HID1 has only read-only information - nothing to set.
312 */
313#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
314 HID0_IFEM|HID0_ABE)
315#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
316#define CFG_HID2 0
317
318/*-----------------------------------------------------------------------
319 * RMR - Reset Mode Register 5-5
320 *-----------------------------------------------------------------------
321 * turn on Checkstop Reset Enable
322 */
323#define CFG_RMR RMR_CSRE
324
325/*-----------------------------------------------------------------------
326 * BCR - Bus Configuration 4-25
327 *-----------------------------------------------------------------------
328 */
329
330#define BCR_APD01 0x10000000
331#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
332
333/*-----------------------------------------------------------------------
334 * SIUMCR - SIU Module Configuration 4-31
335 *-----------------------------------------------------------------------
336 */
337#if 0
338#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
339#else
340#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
341#endif
342
343
344/*-----------------------------------------------------------------------
345 * SYPCR - System Protection Control 4-35
346 * SYPCR can only be written once after reset!
347 *-----------------------------------------------------------------------
348 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
349 */
350#if defined(CONFIG_WATCHDOG)
351#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
352 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
353#else
354#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
355 SYPCR_SWRI|SYPCR_SWP)
356#endif /* CONFIG_WATCHDOG */
357
358/*-----------------------------------------------------------------------
359 * TMCNTSC - Time Counter Status and Control 4-40
360 *-----------------------------------------------------------------------
361 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
362 * and enable Time Counter
363 */
364#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
365
366/*-----------------------------------------------------------------------
367 * PISCR - Periodic Interrupt Status and Control 4-42
368 *-----------------------------------------------------------------------
369 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
370 * Periodic timer
371 */
372#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
373
374/*-----------------------------------------------------------------------
375 * SCCR - System Clock Control 9-8
376 *-----------------------------------------------------------------------
377 */
378#define CFG_SCCR (SCCR_DFBRG01)
379
380/*-----------------------------------------------------------------------
381 * RCCR - RISC Controller Configuration 13-7
382 *-----------------------------------------------------------------------
383 */
384#define CFG_RCCR 0
385
386/*
387 * Init Memory Controller:
388 *
389 * Bank Bus Machine PortSz Device
390 * ---- --- ------- ------ ------
391 * 0 60x GPCM 64 bit FLASH
392 * 1 60x SDRAM 64 bit SDRAM
393 * 2 Local SDRAM 32 bit SDRAM
394 *
395 */
396
397 /* Initialize SDRAM on local bus
398 */
399#define CFG_INIT_LOCAL_SDRAM
400
401
402/* Minimum mask to separate preliminary
403 * address ranges for CS[0:2]
404 */
405#define CFG_MIN_AM_MASK 0xC0000000
406
407#define CFG_MPTPR 0x1F00
408
409#define CFG_MRS_OFFS 0x00000000
410
411
412#if defined(CONFIG_BOOT_ROM)
413/*
414 * Bank 0 - Boot ROM (8 bit wide)
415 */
416#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
417 BRx_PS_8 |\
418 BRx_MS_GPCM_P |\
419 BRx_V)
420
421#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
422 ORxG_CSNT |\
423 ORxG_ACS_DIV1 |\
424 ORxG_SCY_3_CLK |\
425 ORxG_EHTR |\
426 ORxG_TRLX)
427
428/*
429 * Bank 1 - Flash (64 bit wide)
430 */
431#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
432 BRx_PS_64 |\
433 BRx_MS_GPCM_P |\
434 BRx_V)
435
436#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
437 ORxG_CSNT |\
438 ORxG_ACS_DIV1 |\
439 ORxG_SCY_3_CLK |\
440 ORxG_EHTR |\
441 ORxG_TRLX)
442
443#else /* ! CONFIG_BOOT_ROM */
444
445/*
446 * Bank 0 - Flash (64 bit wide)
447 */
448#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
449 BRx_PS_64 |\
450 BRx_MS_GPCM_P |\
451 BRx_V)
452
453#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
454 ORxG_CSNT |\
455 ORxG_ACS_DIV1 |\
456 ORxG_SCY_3_CLK |\
457 ORxG_EHTR |\
458 ORxG_TRLX)
459
460/*
461 * Bank 1 - Disk-On-Chip
462 */
463#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
464 BRx_PS_8 |\
465 BRx_MS_GPCM_P |\
466 BRx_V)
467
468#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
469 ORxG_CSNT |\
470 ORxG_ACS_DIV1 |\
471 ORxG_SCY_3_CLK |\
472 ORxG_EHTR |\
473 ORxG_TRLX)
474
475#endif /* CONFIG_BOOT_ROM */
476
477/* Bank 2 - SDRAM
478 */
479#define CFG_PSRT 0x0F
480#ifndef CFG_RAMBOOT
481#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
482 BRx_PS_64 |\
483 BRx_MS_SDRAM_P |\
484 BRx_V)
485
486 /* SDRAM initialization values for 8-column chips
487 */
488#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
489 ORxS_BPD_4 |\
490 ORxS_ROWST_PBI0_A9 |\
491 ORxS_NUMR_12)
492
493#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
494 PSDMR_BSMA_A14_A16 |\
495 PSDMR_SDA10_PBI0_A10 |\
496 PSDMR_RFRC_7_CLK |\
497 PSDMR_PRETOACT_2W |\
498 PSDMR_ACTTORW_1W |\
499 PSDMR_LDOTOPRE_1C |\
500 PSDMR_WRC_1C |\
501 PSDMR_CL_2)
502
503 /* SDRAM initialization values for 9-column chips
504 */
505#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
506 ORxS_BPD_4 |\
507 ORxS_ROWST_PBI0_A7 |\
508 ORxS_NUMR_13)
509
510#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
511 PSDMR_BSMA_A13_A15 |\
512 PSDMR_SDA10_PBI0_A9 |\
513 PSDMR_RFRC_7_CLK |\
514 PSDMR_PRETOACT_2W |\
515 PSDMR_ACTTORW_1W |\
516 PSDMR_LDOTOPRE_1C |\
517 PSDMR_WRC_1C |\
518 PSDMR_CL_2)
519
520#define CFG_OR2_PRELIM CFG_OR2_9COL
521#define CFG_PSDMR CFG_PSDMR_9COL
522
523#endif /* CFG_RAMBOOT */
524
525#endif /* __CONFIG_H */